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Thu, 26 Nov 2020 10:36:03 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3215852054; Thu, 26 Nov 2020 10:36:03 +0000 (GMT) Received: from [9.199.35.78] (unknown [9.199.35.78]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 569D952050; Thu, 26 Nov 2020 10:36:01 +0000 (GMT) Subject: Re: [PATCH 1/2] powerpc: sstep: Fix load and update instructions To: Sandipan Das , mpe@ellerman.id.au References: <20201119054139.244083-1-sandipan@linux.ibm.com> From: Ravi Bangoria Message-ID: Date: Thu, 26 Nov 2020 16:06:00 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: <20201119054139.244083-1-sandipan@linux.ibm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-26_03:2020-11-26, 2020-11-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 phishscore=0 spamscore=0 malwarescore=0 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011260060 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ravi Bangoria , jniethe5@gmail.com, paulus@samba.org, naveen.n.rao@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org, dja@axtens.net Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 11/19/20 11:11 AM, Sandipan Das wrote: > The Power ISA says that the fixed-point load and update > instructions must neither use R0 for the base address (RA) > nor have the destination (RT) and the base address (RA) as > the same register. In these cases, the instruction is > invalid. This applies to the following instructions. > * Load Byte and Zero with Update (lbzu) > * Load Byte and Zero with Update Indexed (lbzux) > * Load Halfword and Zero with Update (lhzu) > * Load Halfword and Zero with Update Indexed (lhzux) > * Load Halfword Algebraic with Update (lhau) > * Load Halfword Algebraic with Update Indexed (lhaux) > * Load Word and Zero with Update (lwzu) > * Load Word and Zero with Update Indexed (lwzux) > * Load Word Algebraic with Update Indexed (lwaux) > * Load Doubleword with Update (ldu) > * Load Doubleword with Update Indexed (ldux) > > However, the following behaviour is observed using some > invalid opcodes where RA = RT. > > An userspace program using an invalid instruction word like > 0xe9ce0001, i.e. "ldu r14, 0(r14)", runs and exits without > getting terminated abruptly. The instruction performs the > load operation but does not write the effective address to > the base address register. Attaching an uprobe at that > instruction's address results in emulation which writes the > effective address to the base register. Thus, the final value > of the base address register is different. > > To remove any inconsistencies, this adds an additional check > for the aforementioned instructions to make sure that they > are treated as unknown by the emulation infrastructure when > RA = 0 or RA = RT. The kernel will then fallback to executing > the instruction on hardware. > > Signed-off-by: Sandipan Das For the series: Reviewed-by: Ravi Bangoria