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Fri, 17 Jun 2022 15:24:46 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 665EFAE05F; Fri, 17 Jun 2022 15:24:46 +0000 (GMT) Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5C807AE05C; Fri, 17 Jun 2022 15:24:45 +0000 (GMT) Received: from [9.163.26.91] (unknown [9.163.26.91]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTPS; Fri, 17 Jun 2022 15:24:45 +0000 (GMT) Message-ID: Date: Fri, 17 Jun 2022 12:24:43 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Firefox/91.0 Thunderbird/91.10.0 Subject: Re: [PATCH] KVM: PPC: Align pt_regs in kvm_vcpu_arch structure Content-Language: en-US To: Fabiano Rosas , linuxppc-dev@lists.ozlabs.org References: <20220525124944.2613333-1-farosas@linux.ibm.com> From: =?UTF-8?Q?Murilo_Opsfelder_Ara=c3=bajo?= Organization: IBM In-Reply-To: <20220525124944.2613333-1-farosas@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: _R_-gaHzvFzN5ye1drkMhWqA6ZDiv-Xu X-Proofpoint-ORIG-GUID: NnFCRvfU1eKex2TE8HntQ0-ZAhZw5VYU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-17_10,2022-06-17_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 impostorscore=0 spamscore=0 suspectscore=0 clxscore=1011 phishscore=0 adultscore=0 mlxlogscore=999 malwarescore=0 priorityscore=1501 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206170065 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: muriloo@linux.ibm.com Cc: kvm-ppc@vger.kernel.org, npiggin@gmail.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Hi, Fabiano. On 5/25/22 09:49, Fabiano Rosas wrote: > The H_ENTER_NESTED hypercall receives as second parameter the address > of a region of memory containing the values for the nested guest > privileged registers. We currently use the pt_regs structure contained > within kvm_vcpu_arch for that end. > > Most hypercalls that receive a memory address expect that region to > not cross a 4k page boundary. We would want H_ENTER_NESTED to follow > the same pattern so this patch ensures the pt_regs structure sits > within a page. > > Signed-off-by: Fabiano Rosas Is it necessary to explain in the commit message that even though the second parameter needs to be 4k-aligned, we're aligning pt_regs to 512 bytes so it can be placed within a 4k boundary because its size is below 512 bytes? The natural thinking would be aligning it to 4k bytes, which would punch a huge hole in kvm_vcpu_arch. I think having the explanation of why 512 vs. 4k is worthwhile mentioning. > --- > arch/powerpc/include/asm/kvm_host.h | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h > index faf301d0dec0..87eba60f2920 100644 > --- a/arch/powerpc/include/asm/kvm_host.h > +++ b/arch/powerpc/include/asm/kvm_host.h > @@ -519,7 +519,11 @@ struct kvm_vcpu_arch { > struct kvmppc_book3s_shadow_vcpu *shadow_vcpu; > #endif > > - struct pt_regs regs; > + /* > + * This is passed along to the HV via H_ENTER_NESTED. Align to > + * prevent it crossing a real 4K page. > + */ > + struct pt_regs regs __aligned(512); > > struct thread_fp_state fp; > -- Murilo