From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8908C76196 for ; Fri, 31 Mar 2023 11:03:48 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4Pny8M1RCFz3fV9 for ; Fri, 31 Mar 2023 22:03:47 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aculab.com (client-ip=185.58.86.151; helo=eu-smtp-delivery-151.mimecast.com; envelope-from=david.laight@aculab.com; receiver=) X-Greylist: delayed 64 seconds by postgrey-1.36 at boromir; Fri, 31 Mar 2023 22:03:18 AEDT Received: from eu-smtp-delivery-151.mimecast.com (eu-smtp-delivery-151.mimecast.com [185.58.86.151]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4Pny7p5By6z2yPD for ; Fri, 31 Mar 2023 22:03:18 +1100 (AEDT) Received: from AcuMS.aculab.com (156.67.243.121 [156.67.243.121]) by relay.mimecast.com with ESMTP with both STARTTLS and AUTH (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id uk-mta-61-KKeVLz0_Nn2s0KMUR0InMw-1; Fri, 31 Mar 2023 12:02:05 +0100 X-MC-Unique: KKeVLz0_Nn2s0KMUR0InMw-1 Received: from AcuMS.Aculab.com (10.202.163.4) by AcuMS.aculab.com (10.202.163.4) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 31 Mar 2023 12:01:54 +0100 Received: from AcuMS.Aculab.com ([::1]) by AcuMS.aculab.com ([::1]) with mapi id 15.00.1497.048; Fri, 31 Mar 2023 12:01:54 +0100 From: David Laight To: 'Arnd Bergmann' , Russell King , Arnd Bergmann Subject: RE: [PATCH 15/21] ARM: dma-mapping: always invalidate WT caches before DMA Thread-Topic: [PATCH 15/21] ARM: dma-mapping: always invalidate WT caches before DMA Thread-Index: AQHZY70jODQmP+MmIk+VbheoRzXsQa8Ut5Vg Date: Fri, 31 Mar 2023 11:01:54 +0000 Message-ID: References: <20230327121317.4081816-1-arnd@kernel.org> <20230327121317.4081816-16-arnd@kernel.org> In-Reply-To: Accept-Language: en-GB, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.202.205.107] MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: aculab.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rich Felker , "linux-sh@vger.kernel.org" , Catalin Marinas , Linus Walleij , Paul Walmsley , "linux-kernel@vger.kernel.org" , Max Filippov , "Conor.Dooley" , guoren , "sparclinux@vger.kernel.org" , "linux-riscv@lists.infradead.org" , Will Deacon , Christoph Hellwig , "linux-hexagon@vger.kernel.org" , Helge Deller , "linux-csky@vger.kernel.org" , Geert Uytterhoeven , Vineet Gupta , "linux-snps-arc@lists.infradead.org" , "linux-xtensa@linux-xtensa.org" , Neil Armstrong , "Lad, Prabhakar" , "linux-m68k@lists.linux-m68k.org" , John Paul Adrian Glaubitz , Stafford Horne , "linux-arm-kernel@lists.infradead.org" , Brian Cain , Michal Simek , Thomas Bogendoerfer , "linux-parisc@vger.kernel.org" , "linux-openrisc@vger.kernel.org" , Robin Murphy , "linux-mips@vger.kernel.org" , Dinh Nguyen , Palmer Dabbelt , "linux-oxnas@groups.io" , "linuxppc-dev@lists.ozlabs.org" , "David S . Miller" Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Arnd Bergmann > Sent: 31 March 2023 11:39 ... > Most architectures that have write-through caches (m68k, > microblaze) or write-back caches but no speculation (all other > armv4/armv5, hexagon, openrisc, sh, most mips, later xtensa) > only invalidate before DMA but not after. >=20 > OTOH, most machines that are actually in use today (armv6+, > powerpc, later mips, microblaze, riscv, nios2) also have to > deal with speculative accesses, so they end up having to > invalidate or flush both before and after a DMA_FROM_DEVICE > and DMA_BIDIRECTIONAL. nios2 is a simple in-order cpu with a short pipeline (it is a soft-cpu made from normal fpga logic elements). Definitely doesn't do speculative accesses. OTOH any one trying to run Linux on it needs their head examined. =09David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1= PT, UK Registration No: 1397386 (Wales)