* [PATCH] powerpc: Add gcc 128-bit shift helpers
[not found] <202505152053.FrKekjCe-lkp@intel.com>
@ 2025-05-16 8:46 ` Herbert Xu
2025-05-16 11:06 ` Gabriel Paubert
0 siblings, 1 reply; 3+ messages in thread
From: Herbert Xu @ 2025-05-16 8:46 UTC (permalink / raw)
To: kernel test robot
Cc: oe-kbuild-all, Linux Crypto Mailing List, Venkat Rao Bagalkote,
Madhavan Srinivasan, Stephen Rothwell, Danny Tsen, linuxppc-dev,
Michael Ellerman
On Thu, May 15, 2025 at 08:06:09PM +0800, kernel test robot wrote:
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> head: 484803582c77061b470ac64a634f25f89715be3f
> commit: c66d7ebbe2fa14e41913adb421090a7426f59786 [10914/11408] crypto: powerpc/poly1305 - Add SIMD fallback
> config: powerpc64-randconfig-002-20250515 (https://download.01.org/0day-ci/archive/20250515/202505152053.FrKekjCe-lkp@intel.com/config)
> compiler: powerpc64-linux-gcc (GCC) 8.5.0
> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250515/202505152053.FrKekjCe-lkp@intel.com/reproduce)
Thanks for the report. This patch should fix the problem.
---8<---
When optimising for size, gcc generates out-of-line calls for 128-bit
integer shifts. Add these functions to avoid build errors.
Fixes: c66d7ebbe2fa ("crypto: powerpc/poly1305 - Add SIMD fallback")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202505152053.FrKekjCe-lkp@intel.com/
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 1cd74673cbf7..a41c071c1652 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -87,3 +87,5 @@ obj-$(CONFIG_CRC_T10DIF_ARCH) += crc-t10dif-powerpc.o
crc-t10dif-powerpc-y := crc-t10dif-glue.o crct10dif-vpmsum_asm.o
obj-$(CONFIG_PPC64) += $(obj64-y)
+
+obj-$(CONFIG_ARCH_SUPPORTS_INT128) += tishift.o
diff --git a/arch/powerpc/lib/tishift.S b/arch/powerpc/lib/tishift.S
new file mode 100644
index 000000000000..79afef2d8d54
--- /dev/null
+++ b/arch/powerpc/lib/tishift.S
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2025 Herbert Xu <herbert@gondor.apana.org.au>
+ */
+#include <asm/ppc_asm.h>
+#include <linux/export.h>
+
+_GLOBAL(__lshrti3)
+ cmplwi r5,63
+ ble 1f
+ addi r5,r5,-64
+ srd r3,r4,r5
+ li r4,0
+ blr
+1:
+ subfic r7,r5,64
+ srd r3,r3,r5
+ sld r6,r4,r7
+ srd r4,r4,r5
+ or r3,r3,r6
+ blr
+EXPORT_SYMBOL(__lshrti3)
+
+_GLOBAL(__ashrti3)
+ cmplwi r5,63
+ ble 1f
+ addi r5,r5,-64
+ srad r3,r4,r5
+ sradi r4,r4,63
+ blr
+1:
+ subfic r7,r5,64
+ srd r3,r3,r5
+ sld r6,r4,r7
+ srad r4,r4,r5
+ or r3,r3,r6
+ blr
+EXPORT_SYMBOL(__ashrti3)
+
+_GLOBAL(__ashlti3)
+ cmplwi r5,63
+ ble 1f
+ addi r5,r5,-64
+ sld r4,r3,r5
+ li r3,0
+ blr
+1:
+ subfic r7,r5,64
+ sld r4,r4,r5
+ srd r6,r3,r7
+ sld r3,r3,r5
+ or r4,r4,r6
+ blr
+EXPORT_SYMBOL(__ashlti3)
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] powerpc: Add gcc 128-bit shift helpers
2025-05-16 8:46 ` [PATCH] powerpc: Add gcc 128-bit shift helpers Herbert Xu
@ 2025-05-16 11:06 ` Gabriel Paubert
2025-05-17 1:50 ` [v2 PATCH] " Herbert Xu
0 siblings, 1 reply; 3+ messages in thread
From: Gabriel Paubert @ 2025-05-16 11:06 UTC (permalink / raw)
To: Herbert Xu
Cc: kernel test robot, oe-kbuild-all, Linux Crypto Mailing List,
Venkat Rao Bagalkote, Madhavan Srinivasan, Stephen Rothwell,
Danny Tsen, linuxppc-dev, Michael Ellerman
On Fri, May 16, 2025 at 04:46:17PM +0800, Herbert Xu wrote:
> On Thu, May 15, 2025 at 08:06:09PM +0800, kernel test robot wrote:
> > tree: https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git__;!!D9dNQwwGXtA!TSuOAutxjuD3Hp-RC0Fw9dTNuagdCKeNLTN71tv_OmhUxyAPLfIfwwpZop5pKFXgS4Jfkt830_tEMkbHT4vfog$ master
> > head: 484803582c77061b470ac64a634f25f89715be3f
> > commit: c66d7ebbe2fa14e41913adb421090a7426f59786 [10914/11408] crypto: powerpc/poly1305 - Add SIMD fallback
> > config: powerpc64-randconfig-002-20250515 (https://urldefense.com/v3/__https://download.01.org/0day-ci/archive/20250515/202505152053.FrKekjCe-lkp@intel.com/config__;!!D9dNQwwGXtA!TSuOAutxjuD3Hp-RC0Fw9dTNuagdCKeNLTN71tv_OmhUxyAPLfIfwwpZop5pKFXgS4Jfkt830_tEMkaPDLMaoA$ )
> > compiler: powerpc64-linux-gcc (GCC) 8.5.0
> > reproduce (this is a W=1 build): (https://urldefense.com/v3/__https://download.01.org/0day-ci/archive/20250515/202505152053.FrKekjCe-lkp@intel.com/reproduce__;!!D9dNQwwGXtA!TSuOAutxjuD3Hp-RC0Fw9dTNuagdCKeNLTN71tv_OmhUxyAPLfIfwwpZop5pKFXgS4Jfkt830_tEMkbNYWK3LQ$ )
>
> Thanks for the report. This patch should fix the problem.
It won't work for big endian, nor for 32 bit obviously.
Besides that, in arch/power/kernel/misc_32.S, you'll find a branchless
version of these functions. It's for 64 bit shifts on 32 bit big-endian
but it can easily be adapted to 128 bit shifts on 64 bit processors
(swapping r3 and r4 depending on endianness).
Several functions of kernel/misc_32.S should arguably be moved to lib/.
Cheers,
Gabriel
>
> ---8<---
> When optimising for size, gcc generates out-of-line calls for 128-bit
> integer shifts. Add these functions to avoid build errors.
>
> Fixes: c66d7ebbe2fa ("crypto: powerpc/poly1305 - Add SIMD fallback")
> Reported-by: kernel test robot <lkp@intel.com>
> Closes: https://urldefense.com/v3/__https://lore.kernel.org/oe-kbuild-all/202505152053.FrKekjCe-lkp@intel.com/__;!!D9dNQwwGXtA!TSuOAutxjuD3Hp-RC0Fw9dTNuagdCKeNLTN71tv_OmhUxyAPLfIfwwpZop5pKFXgS4Jfkt830_tEMkbo7rsvYg$
> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
>
> diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
> index 1cd74673cbf7..a41c071c1652 100644
> --- a/arch/powerpc/lib/Makefile
> +++ b/arch/powerpc/lib/Makefile
> @@ -87,3 +87,5 @@ obj-$(CONFIG_CRC_T10DIF_ARCH) += crc-t10dif-powerpc.o
> crc-t10dif-powerpc-y := crc-t10dif-glue.o crct10dif-vpmsum_asm.o
>
> obj-$(CONFIG_PPC64) += $(obj64-y)
> +
> +obj-$(CONFIG_ARCH_SUPPORTS_INT128) += tishift.o
> diff --git a/arch/powerpc/lib/tishift.S b/arch/powerpc/lib/tishift.S
> new file mode 100644
> index 000000000000..79afef2d8d54
> --- /dev/null
> +++ b/arch/powerpc/lib/tishift.S
> @@ -0,0 +1,54 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * Copyright (c) 2025 Herbert Xu <herbert@gondor.apana.org.au>
> + */
> +#include <asm/ppc_asm.h>
> +#include <linux/export.h>
> +
> +_GLOBAL(__lshrti3)
> + cmplwi r5,63
> + ble 1f
> + addi r5,r5,-64
> + srd r3,r4,r5
> + li r4,0
> + blr
> +1:
> + subfic r7,r5,64
> + srd r3,r3,r5
> + sld r6,r4,r7
> + srd r4,r4,r5
> + or r3,r3,r6
> + blr
> +EXPORT_SYMBOL(__lshrti3)
> +
> +_GLOBAL(__ashrti3)
> + cmplwi r5,63
> + ble 1f
> + addi r5,r5,-64
> + srad r3,r4,r5
> + sradi r4,r4,63
> + blr
> +1:
> + subfic r7,r5,64
> + srd r3,r3,r5
> + sld r6,r4,r7
> + srad r4,r4,r5
> + or r3,r3,r6
> + blr
> +EXPORT_SYMBOL(__ashrti3)
> +
> +_GLOBAL(__ashlti3)
> + cmplwi r5,63
> + ble 1f
> + addi r5,r5,-64
> + sld r4,r3,r5
> + li r3,0
> + blr
> +1:
> + subfic r7,r5,64
> + sld r4,r4,r5
> + srd r6,r3,r7
> + sld r3,r3,r5
> + or r4,r4,r6
> + blr
> +EXPORT_SYMBOL(__ashlti3)
> --
> Email: Herbert Xu <herbert@gondor.apana.org.au>
> Home Page: https://urldefense.com/v3/__http://gondor.apana.org.au/*herbert/__;fg!!D9dNQwwGXtA!TSuOAutxjuD3Hp-RC0Fw9dTNuagdCKeNLTN71tv_OmhUxyAPLfIfwwpZop5pKFXgS4Jfkt830_tEMkbwt6bO1g$
> PGP Key: https://urldefense.com/v3/__http://gondor.apana.org.au/*herbert/pubkey.txt__;fg!!D9dNQwwGXtA!TSuOAutxjuD3Hp-RC0Fw9dTNuagdCKeNLTN71tv_OmhUxyAPLfIfwwpZop5pKFXgS4Jfkt830_tEMkam0aoZDQ$
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* [v2 PATCH] powerpc: Add gcc 128-bit shift helpers
2025-05-16 11:06 ` Gabriel Paubert
@ 2025-05-17 1:50 ` Herbert Xu
0 siblings, 0 replies; 3+ messages in thread
From: Herbert Xu @ 2025-05-17 1:50 UTC (permalink / raw)
To: Gabriel Paubert
Cc: kernel test robot, oe-kbuild-all, Linux Crypto Mailing List,
Venkat Rao Bagalkote, Madhavan Srinivasan, Stephen Rothwell,
Danny Tsen, linuxppc-dev, Michael Ellerman
On Fri, May 16, 2025 at 01:06:54PM +0200, Gabriel Paubert wrote:
>
> It won't work for big endian, nor for 32 bit obviously.
Good catch, I will restrict the Kconfig option to little-endian.
The accelerated crypto code which uses this is already restricted
to little-endian anyway.
The Kconfig option is also dependent on PPC64 so 32-bit shouldn't
be a problem.
> Besides that, in arch/power/kernel/misc_32.S, you'll find a branchless
> version of these functions. It's for 64 bit shifts on 32 bit big-endian
> but it can easily be adapted to 128 bit shifts on 64 bit processors
> (swapping r3 and r4 depending on endianness).
Nice. I've replaced the shift code with one based on misc_32.S.
> Several functions of kernel/misc_32.S should arguably be moved to lib/.
I'll leave that to someone else :)
Thanks,
---8<---
When optimising for size, gcc generates out-of-line calls for 128-bit
integer shifts. Add these functions to avoid build errors.
Also restrict ARCH_SUPPORTS_INT128 to little-endian since the only
user that prompted this poly1305 only supports that.
Fixes: c66d7ebbe2fa ("crypto: powerpc/poly1305 - Add SIMD fallback")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://urldefense.com/v3/__https://lore.kernel.org/oe-kbuild-all/202505152053.FrKekjCe-lkp@intel.com/__;!!D9dNQwwGXtA!TSuOAutxjuD3Hp-RC0Fw9dTNuagdCKeNLTN71tv_OmhUxyAPLfIfwwpZop5pKFXgS4Jfkt830_tEMkbo7rsvYg$
Suggested-by: Gabriel Paubert <paubert@iram.es>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 651e0c32957a..7a7d39fa8b01 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -173,7 +173,7 @@ config PPC
select ARCH_STACKWALK
select ARCH_SUPPORTS_ATOMIC_RMW
select ARCH_SUPPORTS_DEBUG_PAGEALLOC if PPC_BOOK3S || PPC_8xx
- select ARCH_SUPPORTS_INT128 if PPC64 && CC_HAS_INT128
+ select ARCH_SUPPORTS_INT128 if PPC64 && CC_HAS_INT128 && CPU_LITTLE_ENDIAN
select ARCH_USE_BUILTIN_BSWAP
select ARCH_USE_CMPXCHG_LOCKREF if PPC64
select ARCH_USE_MEMTEST
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 1cd74673cbf7..a41c071c1652 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -87,3 +87,5 @@ obj-$(CONFIG_CRC_T10DIF_ARCH) += crc-t10dif-powerpc.o
crc-t10dif-powerpc-y := crc-t10dif-glue.o crct10dif-vpmsum_asm.o
obj-$(CONFIG_PPC64) += $(obj64-y)
+
+obj-$(CONFIG_ARCH_SUPPORTS_INT128) += tishift.o
diff --git a/arch/powerpc/lib/tishift.S b/arch/powerpc/lib/tishift.S
new file mode 100644
index 000000000000..f63748b5e1c5
--- /dev/null
+++ b/arch/powerpc/lib/tishift.S
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
+ * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
+ * and Paul Mackerras.
+ * Copyright (c) 2025 Herbert Xu <herbert@gondor.apana.org.au>
+ */
+#include <asm/ppc_asm.h>
+#include <linux/export.h>
+
+_GLOBAL(__lshrti3)
+ subfic r6,r5,64
+ srd r3,r3,r5 # LSW = count > 63 ? 0 : LSW >> count
+ addi r7,r5,-64 # could be xori, or addi with -64
+ sld r6,r4,r6 # t1 = count > 63 ? 0 : MSW << (64-count)
+ srd r7,r4,r7 # t2 = count < 64 ? 0 : MSW >> (count-64)
+ or r3,r3,r6 # LSW |= t1
+ srd r4,r4,r5 # MSW = MSW >> count
+ or r3,r3,r7 # LSW |= t2
+ blr
+EXPORT_SYMBOL(__lshrti3)
+
+_GLOBAL(__ashrti3)
+ subfic r6,r5,64
+ srd r3,r3,r5 # LSW = count > 63 ? 0 : LSW >> count
+ addi r7,r5,-64 # could be xori, or addi with -64
+ sld r6,r4,r6 # t1 = count > 63 ? 0 : MSW << (64-count)
+ rlwinm r8,r7,0,64 # t3 = (count < 64) ? 64 : 0
+ srad r7,r4,r7 # t2 = MSW >> (count-64)
+ or r3,r3,r6 # LSW |= t1
+ sld r7,r7,r8 # t2 = (count < 64) ? 0 : t2
+ srad r4,r4,r5 # MSW = MSW >> count
+ or r3,r3,r7 # LSW |= t2
+ blr
+EXPORT_SYMBOL(__ashrti3)
+
+_GLOBAL(__ashlti3)
+ subfic r6,r5,64
+ sld r4,r4,r5 # MSW = count > 64 ? 0 : MSW << count
+ addi r7,r5,-64 # could be xori, or addi with -64
+ srd r6,r3,r6 # t1 = count > 63 ? 0 : LSW >> (64-count)
+ sld r7,r3,r7 # t2 = count < 64 ? 0 : LSW << (count-64)
+ or r4,r4,r6 # MSW |= t1
+ sld r3,r3,r5 # LSW = LSW << count
+ or r4,r4,r7 # MSW |= t2
+ blr
+EXPORT_SYMBOL(__ashlti3)
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply related [flat|nested] 3+ messages in thread
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[not found] <202505152053.FrKekjCe-lkp@intel.com>
2025-05-16 8:46 ` [PATCH] powerpc: Add gcc 128-bit shift helpers Herbert Xu
2025-05-16 11:06 ` Gabriel Paubert
2025-05-17 1:50 ` [v2 PATCH] " Herbert Xu
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