From: Crystal Wood <oss@buserror.net>
To: "Rob Herring (Arm)" <robh@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Madhavan Srinivasan <maddy@linux.ibm.com>,
Michael Ellerman <mpe@ellerman.id.au>,
Nicholas Piggin <npiggin@gmail.com>,
Christophe Leroy <christophe.leroy@csgroup.eu>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH] dt-bindings: powerpc: Drop duplicate fsl/mpic.txt
Date: Tue, 12 Aug 2025 03:42:31 -0500 [thread overview]
Message-ID: <aJr-d1tZREOY6U5a@buserror.net> (raw)
In-Reply-To: <20250807214432.4173273-1-robh@kernel.org>
On Thu, Aug 07, 2025 at 04:44:30PM -0500, Rob Herring (Arm) wrote:
> The chrp,open-pic binding schema already supports the "fsl,mpic"
> compatible. A couple of properties are missing, so add them and remove
> fsl/mpic.txt.
>
> Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
What about the 4-cell interrupt specifiers?
> - 0 = external or normal SoC device interrupt
> -
> - The interrupt-number cell contains
> - the SoC device interrupt number. The
> - type-specific cell is undefined. The
> - interrupt-number is derived from the
> - MPIC a block of registers referred to as
> - the "Interrupt Source Configuration Registers".
> - Each source has 32-bytes of registers
> - (vector/priority and destination) in this
> - region. So interrupt 0 is at offset 0x0,
> - interrupt 1 is at offset 0x20, and so on.
FWIW, while this description may seem unnecessarily verbose, it's because
it's different from how Freescale hardware docs numbered the IRQs
(IRQ 16 was "internal IRQ 0", etc).
-Crystal
prev parent reply other threads:[~2025-08-12 9:23 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-07 21:44 [PATCH] dt-bindings: powerpc: Drop duplicate fsl/mpic.txt Rob Herring (Arm)
2025-08-08 15:54 ` Conor Dooley
2025-08-11 17:28 ` Rob Herring (Arm)
2025-08-12 8:42 ` Crystal Wood [this message]
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