From: Johan Hovold <johan@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: linux-pci@vger.kernel.org,
Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>,
Christian Zigotzky <chzigotzky@xenosoft.de>,
FUKAUMI Naoki <naoki@radxa.com>,
Herve Codina <herve.codina@bootlin.com>,
Diederik de Haas <diederik@cknow-tech.com>,
Dragan Simic <dsimic@manjaro.org>,
linuxppc-dev@lists.ozlabs.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH] PCI/ASPM: Enable only L0s and L1 for devicetree platforms
Date: Fri, 24 Oct 2025 17:12:38 +0200 [thread overview]
Message-ID: <aPuXZlaawFmmsLmX@hovoldconsulting.com> (raw)
In-Reply-To: <20251023180645.1304701-1-helgaas@kernel.org>
On Thu, Oct 23, 2025 at 01:06:26PM -0500, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <bhelgaas@google.com>
>
> f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree
> platforms") enabled Clock Power Management and L1 PM Substates, but those
> features depend on CLKREQ# and possibly other device-specific
> configuration. We don't know whether CLKREQ# is supported, so we shouldn't
> blindly enable Clock PM and L1 PM Substates.
>
> Enable only ASPM L0s and L1, and only when both ends of the link advertise
> support for them.
>
> Fixes: f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms")
> Reported-by: Christian Zigotzky <chzigotzky@xenosoft.de>
> Link: https://lore.kernel.org/r/db5c95a1-cf3e-46f9-8045-a1b04908051a@xenosoft.de/
> Reported-by: FUKAUMI Naoki <naoki@radxa.com>
> Closes: https://lore.kernel.org/r/22594781424C5C98+22cb5d61-19b1-4353-9818-3bb2b311da0b@radxa.com/
> Reported-by: Herve Codina <herve.codina@bootlin.com>
> Link: https://lore.kernel.org/r/20251015101304.3ec03e6b@bootlin.com/
> Reported-by: Diederik de Haas <diederik@cknow-tech.com>
> Link: https://lore.kernel.org/r/DDJXHRIRGTW9.GYC2ULZ5WQAL@cknow-tech.com/
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> Tested-by: FUKAUMI Naoki <naoki@radxa.com>
> ---
> I intend this for v6.18-rc3.
Note that this will regress ASPM on Qualcomm platforms further by
disabling L1SS for devices that do not use pwrctrl (e.g. NVMe). ASPM
with pwrctrl is already broken since 6.15. [1]
Reverting also a729c1664619 ("PCI: qcom: Remove custom ASPM enablement
code") should avoid the new regression until a proper fix for the 6.15
regression is in place.
Johan
[1] https://lore.kernel.org/lkml/aH4JPBIk_GEoAezy@hovoldconsulting.com/
next prev parent reply other threads:[~2025-10-24 15:12 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-23 18:06 [PATCH] PCI/ASPM: Enable only L0s and L1 for devicetree platforms Bjorn Helgaas
2025-10-23 18:25 ` Bjorn Helgaas
2025-10-23 19:59 ` Diederik de Haas
2025-10-23 20:39 ` Bjorn Helgaas
2025-10-24 4:28 ` Christian Zigotzky
2025-10-23 18:27 ` Dragan Simic
2025-10-23 20:37 ` Bjorn Helgaas
2025-10-24 15:12 ` Johan Hovold [this message]
2025-10-24 15:20 ` Johan Hovold
2025-10-24 20:39 ` Bjorn Helgaas
2025-10-27 10:00 ` Johan Hovold
2025-10-27 17:12 ` Christian Zigotzky
2025-10-28 23:33 ` Bjorn Helgaas
2025-10-29 5:47 ` Christian Zigotzky
2025-10-29 15:59 ` Bjorn Helgaas
2025-10-29 17:25 ` Bjorn Helgaas
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