From: Frank Li <Frank.li@nxp.com>
To: Niklas Cassel <cassel@kernel.org>
Cc: "Minghuan Lian" <minghuan.Lian@nxp.com>,
"Mingkai Hu" <mingkai.hu@nxp.com>, "Roy Zang" <roy.zang@nxp.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Srikanth Thokala" <srikanth.thokala@intel.com>,
"Thierry Reding" <thierry.reding@gmail.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Kunihiko Hayashi" <hayashi.kunihiko@socionext.com>,
"Masami Hiramatsu" <mhiramat@kernel.org>,
"Marek Vasut" <marek.vasut+renesas@gmail.com>,
"Yoshihiro Shimoda" <yoshihiro.shimoda.uh@renesas.com>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Magnus Damm" <magnus.damm@gmail.com>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Manikanta Maddireddy" <mmaddireddy@nvidia.com>,
"Koichiro Den" <den@valinux.co.jp>,
"Damien Le Moal" <dlemoal@kernel.org>,
linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
linux-arm-msm@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH 1/9] PCI: endpoint: Introduce pci_epc_bar_type BAR_64BIT_UPPER
Date: Tue, 17 Feb 2026 16:57:02 -0500 [thread overview]
Message-ID: <aZTkLiUaMTC7H1kB@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20260217212707.2450423-12-cassel@kernel.org>
On Tue, Feb 17, 2026 at 10:27:07PM +0100, Niklas Cassel wrote:
> Add a pci_epc_bar_type BAR_64BIT_UPPER to more clearly differentiate
> BAR_64BIT_UPPER from BAR_RESERVED.
>
> This BAR type will only be used for a BAR following a "only_64bit" BAR.
>
> This makes the BAR description more clear, and the reader does no longer
> need to check the BAR type for the preceding BAR to know how to interpret
> the BAR type.
>
> No functional changes.
>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> drivers/pci/controller/dwc/pci-layerscape-ep.c | 4 ++--
> drivers/pci/controller/dwc/pcie-keembay.c | 6 +++---
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++--
> drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
> drivers/pci/controller/dwc/pcie-uniphier-ep.c | 10 +++++-----
> drivers/pci/controller/pcie-rcar-ep.c | 6 +++---
> drivers/pci/endpoint/pci-epc-core.c | 3 ++-
> include/linux/pci-epc.h | 5 ++++-
> 8 files changed, 22 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> index a4a800699f89..5a03a8f895f9 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> @@ -251,9 +251,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
> pci->ops = pcie->drvdata->dw_pcie_ops;
>
> ls_epc->bar[BAR_2].only_64bit = true;
> - ls_epc->bar[BAR_3].type = BAR_RESERVED;
> + ls_epc->bar[BAR_3].type = BAR_64BIT_UPPER;
> ls_epc->bar[BAR_4].only_64bit = true;
> - ls_epc->bar[BAR_5].type = BAR_RESERVED;
> + ls_epc->bar[BAR_5].type = BAR_64BIT_UPPER;
> ls_epc->linkup_notifier = true;
>
> pcie->pci = pci;
> diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
> index 2666a9c3d67e..5a00b8cf5b53 100644
> --- a/drivers/pci/controller/dwc/pcie-keembay.c
> +++ b/drivers/pci/controller/dwc/pcie-keembay.c
> @@ -313,11 +313,11 @@ static const struct pci_epc_features keembay_pcie_epc_features = {
> .msi_capable = true,
> .msix_capable = true,
> .bar[BAR_0] = { .only_64bit = true, },
> - .bar[BAR_1] = { .type = BAR_RESERVED, },
> + .bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
> .bar[BAR_2] = { .only_64bit = true, },
> - .bar[BAR_3] = { .type = BAR_RESERVED, },
> + .bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
> .bar[BAR_4] = { .only_64bit = true, },
> - .bar[BAR_5] = { .type = BAR_RESERVED, },
> + .bar[BAR_5] = { .type = BAR_64BIT_UPPER, },
> .align = SZ_16K,
> };
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index 18460f01b2c6..e55675b3840a 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -850,9 +850,9 @@ static const struct pci_epc_features qcom_pcie_epc_features = {
> .msi_capable = true,
> .align = SZ_4K,
> .bar[BAR_0] = { .only_64bit = true, },
> - .bar[BAR_1] = { .type = BAR_RESERVED, },
> + .bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
> .bar[BAR_2] = { .only_64bit = true, },
> - .bar[BAR_3] = { .type = BAR_RESERVED, },
> + .bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
> };
>
> static const struct pci_epc_features *
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 06571d806ab3..31aa9a494dbc 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1993,7 +1993,7 @@ static const struct pci_epc_features tegra_pcie_epc_features = {
> .msi_capable = true,
> .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
> .only_64bit = true, },
> - .bar[BAR_1] = { .type = BAR_RESERVED, },
> + .bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
> .bar[BAR_2] = { .type = BAR_RESERVED, },
> .bar[BAR_3] = { .type = BAR_RESERVED, },
> .bar[BAR_4] = { .type = BAR_RESERVED, },
> diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> index d52753060970..f873a1659592 100644
> --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> @@ -426,9 +426,9 @@ static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
> .msix_capable = false,
> .align = 1 << 16,
> .bar[BAR_0] = { .only_64bit = true, },
> - .bar[BAR_1] = { .type = BAR_RESERVED, },
> + .bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
> .bar[BAR_2] = { .only_64bit = true, },
> - .bar[BAR_3] = { .type = BAR_RESERVED, },
> + .bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
> .bar[BAR_4] = { .type = BAR_RESERVED, },
> .bar[BAR_5] = { .type = BAR_RESERVED, },
> },
> @@ -445,11 +445,11 @@ static const struct uniphier_pcie_ep_soc_data uniphier_nx1_data = {
> .msix_capable = false,
> .align = 1 << 12,
> .bar[BAR_0] = { .only_64bit = true, },
> - .bar[BAR_1] = { .type = BAR_RESERVED, },
> + .bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
> .bar[BAR_2] = { .only_64bit = true, },
> - .bar[BAR_3] = { .type = BAR_RESERVED, },
> + .bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
> .bar[BAR_4] = { .only_64bit = true, },
> - .bar[BAR_5] = { .type = BAR_RESERVED, },
> + .bar[BAR_5] = { .type = BAR_64BIT_UPPER, },
> },
> };
>
> diff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c
> index 657875ef4657..9b3f5391fabe 100644
> --- a/drivers/pci/controller/pcie-rcar-ep.c
> +++ b/drivers/pci/controller/pcie-rcar-ep.c
> @@ -440,13 +440,13 @@ static const struct pci_epc_features rcar_pcie_epc_features = {
> /* use 64-bit BARs so mark BAR[1,3,5] as reserved */
> .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = 128,
> .only_64bit = true, },
> - .bar[BAR_1] = { .type = BAR_RESERVED, },
> + .bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
> .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = 256,
> .only_64bit = true, },
> - .bar[BAR_3] = { .type = BAR_RESERVED, },
> + .bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
> .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256,
> .only_64bit = true, },
> - .bar[BAR_5] = { .type = BAR_RESERVED, },
> + .bar[BAR_5] = { .type = BAR_64BIT_UPPER, },
> };
>
> static const struct pci_epc_features*
> diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
> index 068155819c57..8de321e1c342 100644
> --- a/drivers/pci/endpoint/pci-epc-core.c
> +++ b/drivers/pci/endpoint/pci-epc-core.c
> @@ -104,7 +104,8 @@ enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
>
> for (i = bar; i < PCI_STD_NUM_BARS; i++) {
> /* If the BAR is not reserved, return it. */
> - if (epc_features->bar[i].type != BAR_RESERVED)
> + if (epc_features->bar[i].type != BAR_RESERVED &&
> + epc_features->bar[i].type != BAR_64BIT_UPPER)
> return i;
> }
>
> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
> index c021c7af175f..c22f8a6cf9a3 100644
> --- a/include/linux/pci-epc.h
> +++ b/include/linux/pci-epc.h
> @@ -192,12 +192,15 @@ struct pci_epc {
> * NOTE: An EPC driver can currently only set a single supported
> * size.
> * @BAR_RESERVED: The BAR should not be touched by an EPF driver.
> + * @BAR_64BIT_UPPER: Should only be set on a BAR if the preceding BAR is marked
> + * as only_64bit.
> */
> enum pci_epc_bar_type {
> BAR_PROGRAMMABLE = 0,
> BAR_FIXED,
> BAR_RESIZABLE,
> BAR_RESERVED,
> + BAR_64BIT_UPPER,
> };
>
> /**
> @@ -207,7 +210,7 @@ enum pci_epc_bar_type {
> * @only_64bit: if true, an EPF driver is not allowed to choose if this BAR
> * should be configured as 32-bit or 64-bit, the EPF driver must
> * configure this BAR as 64-bit. Additionally, the BAR succeeding
> - * this BAR must be set to type BAR_RESERVED.
> + * this BAR must be set to type BAR_64BIT_UPPER.
> *
> * only_64bit should not be set on a BAR of type BAR_RESERVED.
> * (If BARx is a 64-bit BAR that an EPF driver is not allowed to
> --
> 2.53.0
>
next prev parent reply other threads:[~2026-02-17 21:57 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-17 21:27 [PATCH 0/9] PCI: endpoint differentiate between disabled and reserved BARs Niklas Cassel
2026-02-17 21:27 ` [PATCH 1/9] PCI: endpoint: Introduce pci_epc_bar_type BAR_64BIT_UPPER Niklas Cassel
2026-02-17 21:57 ` Frank Li [this message]
2026-02-23 3:57 ` Manikanta Maddireddy
2026-02-23 10:14 ` Geert Uytterhoeven
2026-02-24 13:54 ` Manikanta Maddireddy
2026-02-17 21:27 ` [PATCH 6/9] PCI: dwc: Disable BARs in common code instead of in each glue driver Niklas Cassel
2026-02-17 23:00 ` Frank Li
2026-02-23 4:55 ` Manikanta Maddireddy
2026-02-23 3:49 ` [PATCH 0/9] PCI: endpoint differentiate between disabled and reserved BARs Manikanta Maddireddy
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