[PATCH] Adapt spi_mpc83xx SPI driver for 832x

* [PATCH] Adapt spi_mpc83xx SPI driver for 832x
@ 2006-12-13  9:22 Joakim Tjernlund
  2006-12-13  9:44 ` Vitaly Wool
                   ` (2 more replies)
  0 siblings, 3 replies; 9+ messages in thread
From: Joakim Tjernlund @ 2006-12-13  9:22 UTC (permalink / raw)
  To: linuxppc-dev

[-- Attachment #1: Type: text/plain, Size: 290 bytes --]

The MPC 832x has a different SPI controller i/f, probably due to
its QUICC engine support. This patch adapts the spi_mpx83xx driver to
be usable on QE based 83xx cpus.

 Jocke

PS.
   Sorry for the attatcment, I have yet to figure out how to tell
   evolution not to mangle inline patches.

[-- Attachment #2: spi2.diff --]
[-- Type: text/x-patch, Size: 2451 bytes --]

diff --git a/drivers/spi/spi_mpc83xx.c b/drivers/spi/spi_mpc83xx.c
index ff0b048..18f094e 100644
--- a/drivers/spi/spi_mpc83xx.c
+++ b/drivers/spi/spi_mpc83xx.c
@@ -47,13 +47,19 @@ struct mpc83xx_spi_reg {
 #define	SPMODE_ENABLE		(1 << 24)
 #define	SPMODE_LEN(x)		((x) << 20)
 #define	SPMODE_PM(x)		((x) << 16)
+#define	SPMODE_OP		(1 << 14)
 
 /*
  * Default for SPI Mode:
  * 	SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
  */
-#define	SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
-			 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
+#define SPMODE_COMMON_INIT SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
+			   SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf)
+#ifdef CONFIG_QUICC_ENGINE
+  #define SPMODE_INIT_VAL (SPMODE_COMMON_INIT | SPMODE_OP)
+#else
+  #define SPMODE_INIT_VAL (SPMODE_COMMON_INIT)
+#endif
 
 /* SPIE register values */
 #define	SPIE_NE		0x00000200	/* Not empty */
@@ -99,31 +105,39 @@ static inline u32 mpc83xx_spi_read_reg(_
 	return in_be32(reg);
 }
 
-#define MPC83XX_SPI_RX_BUF(type) 					  \
+#define MPC83XX_SPI_RX_BUF(type, shift)					  \
 void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
 {									  \
 	type * rx = mpc83xx_spi->rx;					  \
-	*rx++ = (type)data;						  \
+	*rx++ = (type)(data >> shift);					  \
 	mpc83xx_spi->rx = rx;						  \
 }
 
-#define MPC83XX_SPI_TX_BUF(type)				\
+#define MPC83XX_SPI_TX_BUF(type, shift)				\
 u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi)	\
 {								\
 	u32 data;						\
 	const type * tx = mpc83xx_spi->tx;			\
-	data = *tx++;						\
+	data = *tx++ << shift;					\
 	mpc83xx_spi->tx = tx;					\
 	return data;						\
 }
-
-MPC83XX_SPI_RX_BUF(u8)
-MPC83XX_SPI_RX_BUF(u16)
-MPC83XX_SPI_RX_BUF(u32)
-MPC83XX_SPI_TX_BUF(u8)
-MPC83XX_SPI_TX_BUF(u16)
-MPC83XX_SPI_TX_BUF(u32)
-
+#ifdef CONFIG_QUICC_ENGINE
+/* This assumes SPMODE_REV is set */
+MPC83XX_SPI_RX_BUF(u8, 16)
+MPC83XX_SPI_RX_BUF(u16, 16)
+MPC83XX_SPI_RX_BUF(u32, 0)
+MPC83XX_SPI_TX_BUF(u8, 24)
+MPC83XX_SPI_TX_BUF(u16, 16)
+MPC83XX_SPI_TX_BUF(u32, 0)
+#else
+MPC83XX_SPI_RX_BUF(u8, 0)
+MPC83XX_SPI_RX_BUF(u16, 0)
+MPC83XX_SPI_RX_BUF(u32, 0)
+MPC83XX_SPI_TX_BUF(u8, 0)
+MPC83XX_SPI_TX_BUF(u16, 0)
+MPC83XX_SPI_TX_BUF(u32, 0)
+#endif
 static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
 {
 	struct mpc83xx_spi *mpc83xx_spi;

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