From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3rgmxf094szDqlN for ; Fri, 1 Jul 2016 16:40:21 +1000 (AEST) Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id u616dYJ4140753 for ; Fri, 1 Jul 2016 02:40:20 -0400 Received: from e23smtp09.au.ibm.com (e23smtp09.au.ibm.com [202.81.31.142]) by mx0a-001b2d01.pphosted.com with ESMTP id 23whjc36m3-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 01 Jul 2016 02:40:19 -0400 Received: from localhost by e23smtp09.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 1 Jul 2016 16:40:17 +1000 Received: from d23relay06.au.ibm.com (d23relay06.au.ibm.com [9.185.63.219]) by d23dlp01.au.ibm.com (Postfix) with ESMTP id DF2912CE8046 for ; Fri, 1 Jul 2016 16:40:14 +1000 (EST) Received: from d23av06.au.ibm.com (d23av06.au.ibm.com [9.190.235.151]) by d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u616eEOJ12124488 for ; Fri, 1 Jul 2016 16:40:14 +1000 Received: from d23av06.au.ibm.com (localhost [127.0.0.1]) by d23av06.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u616eEPs010429 for ; Fri, 1 Jul 2016 16:40:14 +1000 Subject: Re: [PATCH v3 2/7] PCI: Ignore enforced alignment to VF BARs To: Gavin Shan References: <1467283993-3185-1-git-send-email-xyjxie@linux.vnet.ibm.com> <1467283993-3185-3-git-send-email-xyjxie@linux.vnet.ibm.com> <20160701003959.GB15147@gwshan> <21112bd7-d343-46b6-1df1-b20cc1c1b24e@linux.vnet.ibm.com> <20160701060519.GA8863@gwshan> Cc: nikunj@linux.vnet.ibm.com, zhong@linux.vnet.ibm.com, linux-doc@vger.kernel.org, aik@ozlabs.ru, linux-pci@vger.kernel.org, corbet@lwn.net, linux-kernel@vger.kernel.org, bhelgaas@google.com, alex.williamson@redhat.com, paulus@samba.org, warrier@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org From: Yongji Xie Date: Fri, 1 Jul 2016 14:40:16 +0800 MIME-Version: 1.0 In-Reply-To: <20160701060519.GA8863@gwshan> Content-Type: text/plain; charset=utf-8; format=flowed Message-Id: List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Hi Gavin, On 2016/7/1 14:05, Gavin Shan wrote: > On Fri, Jul 01, 2016 at 01:27:17PM +0800, Yongji Xie wrote: >>> On Thu, Jun 30, 2016 at 06:53:08PM +0800, Yongji Xie wrote: >>>> VF BARs are read-only zeroes according to SRIOV spec, >>>> the normal way(writing BARs) of allocating resources wouldn't >>>> be applied to VFs. The VFs' resources would be allocated >>>> when we enable SR-IOV capability. So we should not try to >>>> reassign alignment after we enable VFs. It's meaningless >>>> and will release the allocated resources which leads to a bug. >>>> >>>> Signed-off-by: Yongji Xie >>>> --- >>>> drivers/pci/pci.c | 4 ++++ >>>> 1 file changed, 4 insertions(+) >>>> >>>> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c >>>> index be8f72c..6ae02de 100644 >>>> --- a/drivers/pci/pci.c >>>> +++ b/drivers/pci/pci.c >>>> @@ -4822,6 +4822,10 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev) >>>> resource_size_t align, size; >>>> u16 command; >>>> >>>> + /* We should never try to reassign VF's alignment */ >>>> + if (dev->is_virtfn) >>>> + return; >>>> + >>> Yongji, I think it's correct to ignore VF's BARs. Another concern is: >>> it's safe to apply alignment to PF's IOV BARs? Lets have an extreme >>> example here: one PF has 16 VFs; each VF has only one 1KB. It means >>> the only PF IOV BAR is 16KB. I don't see how it works after expanding >>> it to 64KB which is the page size. It might be not a problem on PowerNV >>> platform, but potentially a issue on x86? >> Seems like the alignment would not be applied to IOV BARs because >> pci_reassigndev_resource_alignment() will be called before >> sriov_init(). >> > Correct, thanks for the claim. I guess the alignment applied to PF IOV > BARs should be ignored as well? Anyway, the IOV BARs are retireved from > SRIOV capability. It deserves a comment if you plan to take the change. > Actually, the comment here (for ignoring alignment to VF BARs) can be > improved a bit as well, it'd better why the alignment cannot be applied. > Do you mean we should ignore PF IOV BARs like this: --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4833,7 +4833,7 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev) command &= ~PCI_COMMAND_MEMORY; pci_write_config_word(dev, PCI_COMMAND, command); - for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { + for (i = 0; i <= PCI_ROM_RESOURCE; i++) { r = &dev->resource[i]; if (!(r->flags & IORESOURCE_MEM)) continue; Thanks, Yongji