From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from sj-iport-5.cisco.com (sj-iport-5.cisco.com [171.68.10.87]) by ozlabs.org (Postfix) with ESMTP id ECCE167A05 for ; Wed, 10 May 2006 04:36:10 +1000 (EST) To: Shirley Ma Subject: Re: [openib-general] Re: [PATCH 07/16] ehca: interrupt handling routines References: From: Roland Dreier Date: Tue, 09 May 2006 11:36:07 -0700 In-Reply-To: (Shirley Ma's message of "Tue, 9 May 2006 11:27:29 -0700") Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: linux-kernel@vger.kernel.org, openib-general@openib.org, linuxppc-dev@ozlabs.org, Christoph Raisch , Hoang-Nam Nguyen , Marcus Eder , openib-general-bounces@openib.org, "Michael S. Tsirkin" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Shirley> I have done some patch like that on top of splitting Shirley> CQ. The problem I found that hardware interrupt favors Shirley> one CPU. Most of the time these two threads are running Shirley> on the same cpu according to my debug output. You can Shirley> easily find out by cat /proc/interrupts and Shirley> /proc/irq/XXX/smp_affinity. ehca has distributed Shirley> interrupts evenly on SMP, so it gets the benefits of two Shirley> threads, and gains much better throughputs. Yes, an interrupt will likely be delivered to one CPU. But there's no reason why the two threads can't be pinned to different CPUs or given exclusive CPU masks, exactly the same way that ehca implements it. - R.