From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from sj-iport-6.cisco.com (sj-iport-6.cisco.com [171.71.176.117]) (using TLSv1 with cipher RC4-SHA (128/128 bits)) (Client CN "sj-iport-6.cisco.com", Issuer "Cisco SSCA" (not verified)) by ozlabs.org (Postfix) with ESMTPS id A0C78DDF73 for ; Thu, 28 Aug 2008 10:21:57 +1000 (EST) From: Roland Dreier To: vb Subject: Re: mmap and ppc460gt References: <200808271013.18659.arnd@arndb.de> Date: Wed, 27 Aug 2008 17:11:14 -0700 In-Reply-To: (vb@vsbe.com's message of "Wed, 27 Aug 2008 16:13:52 -0700") Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Arnd Bergmann , linuxppc-embedded@ozlabs.org List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , > The problem now is that that PCI register space gets mapped with > caching enabled (by looking at the TLB contents), so I still can't > control the device. I did some search and indeed UIO device driver > came up, I'll read the article. I was wondering though if there is a > simpler way to modify cache attributes of a region. mmap() doesn't > seem to provide an interface for that, is there some other function to > call to configure 'cache inhibit' attribute for a region? The issue would be related to phys_mem_access_prot() not doing the right thing in this case. In fact it looks like the arch/powerpc page_is_ram() implementation has the same bug that I fixed a long time ago for arch/ppc in 8b150478 ("[PATCH] ppc: make phys_mem_access_prot() work with pfns instead of addresses"). I'll send a patch a little later that you can try out. - R.