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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 10 Sep 2019 09:48:56 +0100 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x8A8mUXv39977248 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 10 Sep 2019 08:48:30 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 24DCE11C04A; Tue, 10 Sep 2019 08:48:55 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EF2D311C04C; Tue, 10 Sep 2019 08:48:51 +0000 (GMT) Received: from [9.204.130.183] (unknown [9.204.130.183]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 10 Sep 2019 08:48:51 +0000 (GMT) Subject: Re: [PATCH v5 21/31] powernv/fadump: process architected register state data provided by firmware To: "Oliver O'Halloran" References: <156630261682.8896.3418665808003586786.stgit@hbathini.in.ibm.com> <156630280239.8896.11769233860624935762.stgit@hbathini.in.ibm.com> <87sgpcp80n.fsf@mpe.ellerman.id.au> From: Hari Bathini Date: Tue, 10 Sep 2019 14:18:50 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 x-cbid: 19091008-0016-0000-0000-000002A96986 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19091008-0017-0000-0000-00003309EF01 Message-Id: X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-09-10_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1906280000 definitions=main-1909100088 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ananth N Mavinakayanahalli , Mahesh J Salgaonkar , Vasant Hegde , linuxppc-dev , Nicholas Piggin , Daniel Axtens Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 09/09/19 9:03 PM, Oliver O'Halloran wrote: > On Mon, Sep 9, 2019 at 11:23 PM Hari Bathini wrote: >> >> On 04/09/19 5:50 PM, Michael Ellerman wrote: >>> Hari Bathini writes: >>> >> >> [...] >> >>>> +/* >>>> + * CPU state data is provided by f/w. Below are the definitions >>>> + * provided in HDAT spec. Refer to latest HDAT specification for >>>> + * any update to this format. >>>> + */ >>> >>> How is this meant to work? If HDAT ever changes the format they will >>> break all existing kernels in the field. >>> >>>> +#define HDAT_FADUMP_CPU_DATA_VERSION 1 >> >> Changes are not expected here. But this is just to cover for such scenario, >> if that ever happens. > > The HDAT spec doesn't define the SPR numbers for NIA, MSR and the CR. > As far as I can tell the values you've assumed here are chip-specific, > non-architected SPR numbers that come from an array buried somewhere > in the SBE codebase. I don't believe you for a second when you say > that this will never change. At least, the understanding is that this numbers not change across processor generations. If something changes, it is supposed to be handled in SBE. Also, I am told this numbers would be listed in the HDAT Spec. Not sure if that happened yet though. Vasant, you have anything to add? >> Also, I think it is a bit far-fetched to error out if versions mismatch. >> Warning and proceeding sounds worthier because the changes are usually >> backward compatible, if and when there are any. Will update accordingly... > > Literally the only reason I didn't drop the CPU DATA parts of the OPAL > MPIPL series was because I assumed the kernel would do the sensible > thing and reject or ignore the structure if it did not know how to > parse the data. I think, the changes if any, would have to be backward compatible for the sake of sanity. Even if they are not, we are better off exporting the /proc/vmcore with a warning and some crazy CPU register data (if parsing goes alright) than no dump at all? - Hari