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Fri, 29 May 2026 10:15:25 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay04.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 64TAFMWe8454638 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 29 May 2026 10:15:22 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E223F20040; Fri, 29 May 2026 10:15:21 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 438582004B; Fri, 29 May 2026 10:15:19 +0000 (GMT) Received: from linux.ibm.com (unknown [9.126.150.29]) by smtpav03.fra02v.mail.ibm.com (Postfix) with SMTP; Fri, 29 May 2026 10:15:19 +0000 (GMT) Date: Fri, 29 May 2026 15:45:18 +0530 From: Srikar Dronamraju To: Shrikanth Hegde Cc: maddy@linux.ibm.com, linuxppc-dev@lists.ozlabs.org, peterz@infradead.org, mingo@kernel.org, christophe.leroy@csgroup.eu, linux-kernel@vger.kernel.org, venkat88@linux.ibm.com, yu.c.chen@intel.com, tim.c.chen@linux.intel.com, kprateek.nayak@amd.com, riteshh@linux.ibm.com, stable@vger.kernel.org, "Ritesh Harjani (IBM)" Subject: Re: [PATCH] sched/topology: Provide arch_llc_mask for cache aware scheduling Message-ID: Reply-To: Srikar Dronamraju References: <20260529075712.1181039-1-sshegde@linux.ibm.com> X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: <20260529075712.1181039-1-sshegde@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=fIYJG5ae c=1 sm=1 tr=0 ts=6a19673f cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=8nJEP1OIZ-IA:10 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VwQbUJbxAAAA:8 a=VnNF1IyMAAAA:8 a=QyXUC8HyAAAA:8 a=pGLkceISAAAA:8 a=UZhIc3m1dWDYcD9tvD4A:9 a=wPNLvfGTeEIA:10 X-Proofpoint-ORIG-GUID: 84M-2t6QsD-y15zqN6r6FdqxPN0jhaF7 X-Proofpoint-GUID: nwXy-Tm7YMjuiWDOdsK30iKORNlUITXV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI5MDEwMCBTYWx0ZWRfX0hnZS8YC9wVD QYHyvNoXC7jpVx4jT4ZppDeHTeUMTEG44HcJCPGjY+X5k35NAcp+lgDjS9Xeuiquo0i5OVPf3Ug F6AOhd1y6Oq21MPVjdqXIAkeUaeeY57mmSS+NZsLEmKlvGS5B33iW+C+L0IWfiZOpVl17AI4k4b RXNnyJT005qyFGtXLiOFx83jHP9aA3mfQaMQTYz2bxWVUbFp3gS2QnWs5+OK4TgIVvp/HoAfmjg 2VJZI7snZylAcFPpQOhcpR/IznVm8dl+7Z8orZurntX1Egwqp6XW+y5z56fO677L3Hs4/wH0QUi BRPaZ+DfXzeIB9DUoVEea2OJcsltl8vPbIEgWQEk5zISDLuP63EzQbQTfOLN5iDt0ANLCWVMikV PF0C5JpQp716vfHUbKuAteErBIZSo+lpNJ3qPyP04597c1KeKpVEvy6dBOh6gERYwIAqLk0k/WA wO4C6zDxnCtrYIiO5UA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-29_03,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 clxscore=1011 adultscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605290100 * Shrikanth Hegde [2026-05-29 13:27:12]: > Venkat Reported a boot kernel panic next-20260522. Git bisect pointed to > b5ea300a17e3 ("sched/cache: Make LLC id continuous") > > Stacktrace points to llc_mask being null. > > NIP [c000000000e58504] _find_first_bit+0x44/0x130 > LR [c000000000e58500] _find_first_bit+0x40/0x130 > Call Trace: > build_sched_domains+0xad8/0xe50 > sched_init_smp+0xa8/0x164 > kernel_init_freeable+0x250/0x370 > ret_from_kernel_user_thread+0x14/0x1c > > On powerpc, cpu_coregroup_mask is available only when the underlying > hardware support coregroup. In shared LPAR, QEMU guest or power9 etc > coregroup isn't supported. In such cases llc_mask was being referenced > when it was null leading to panic. > > On powerpc, LLC is at SMT core level. So assumption that coregroup(MC) > domain point to LLC is wrong. Provide a way for archs to say where its > LLC is if it not at MC domain. > > Based on tip/master at 5c89783224e9 ("Merge branch into tip/master: 'x86/tdx'") > Cc: stable@vger.kernel.org > > Fixes: b5ea300a17e3 ("sched/cache: Make LLC id continuous") > Reported-by: Venkat Rao Bagalkote > Closes: https://lore.kernel.org/all/51154de7-3700-4cb4-82f2-1b3a8fa427f7@linux.ibm.com/ > Reviewed-by: Chen Yu > Tested-by: Venkat Rao Bagalkote > Tested-by: Ritesh Harjani (IBM) > Co-developed-by: Chen, Yu C > Signed-off-by: Shrikanth Hegde > --- > arch/powerpc/include/asm/topology.h | 6 ++++++ > kernel/sched/topology.c | 13 +++++++++++-- > 2 files changed, 17 insertions(+), 2 deletions(-) > > diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h > index 66ed5fe1b718..e3de0f3d8b86 100644 > --- a/arch/powerpc/include/asm/topology.h > +++ b/arch/powerpc/include/asm/topology.h > @@ -135,6 +135,12 @@ struct cpumask *cpu_coregroup_mask(int cpu); > const struct cpumask *cpu_die_mask(int cpu); > int cpu_die_id(int cpu); > > +/* Points to where the LLC is. On power9 this will point at CACHE > + * domain, On others it will point to SMT domain. In all cases > + * cpu_l2_cache_mask points to where LLC is > + */ Nit: Regular comment style could have been better. > +#define arch_llc_mask(cpu) cpu_l2_cache_mask(cpu) > + > #ifdef CONFIG_PPC64 > #include > > diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c > index df2ceb54c970..622e2e01974c 100644 > --- a/kernel/sched/topology.c > +++ b/kernel/sched/topology.c > @@ -2063,12 +2063,21 @@ const struct cpumask *tl_mc_mask(struct sched_domain_topology_level *tl, int cpu > return cpu_coregroup_mask(cpu); > } > > -#define llc_mask(cpu) cpu_coregroup_mask(cpu) > +/* > + * Majority of architectures have LLC at MC domain level with exception > + * such as powerpc. Provide a way for arch to specify where its LLC is > + * if it falls in exception category > + */ > +# ifndef arch_llc_mask > +#define arch_llc_mask(cpu) cpu_coregroup_mask(cpu) > +# endif > > #else > -#define llc_mask(cpu) cpumask_of(cpu) > +#define arch_llc_mask(cpu) cpumask_of(cpu) > #endif > > +#define llc_mask(cpu) arch_llc_mask(cpu) > + Instead of having another define, could we have modified current users of llc_mask() to arch_llc_mask()? Again its not a problem, but why have 2 defines since both point to the same thing. > const struct cpumask *tl_pkg_mask(struct sched_domain_topology_level *tl, int cpu) > { > return cpu_node_mask(cpu); > -- > 2.47.3 > Otherwise, looks good to me. Reviewed-by: Srikar Dronamraju -- Thanks and Regards Srikar Dronamraju