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Sun, 11 Oct 2026 02:45:19 -0700 (PDT) Received: from milan ([2001:9b1:d5a0:a500::24b]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c31a9ad0ad1sm347200666b.77.2026.10.11.02.45.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Oct 2026 02:45:19 -0700 (PDT) From: Uladzislau Rezki X-Google-Original-From: Uladzislau Rezki Date: Sun, 11 Oct 2026 11:45:16 +0200 To: ryan.roberts@arm.com, dev.jain@arm.com Cc: akpm@linux-foundation.org, catalin.marinas@arm.com, linux-mm@kvack.org, urezki@gmail.com, will@kernel.org, Xueyuan.chen21@gmail.com, ajd@linux.ibm.com, anshuman.khandual@arm.com, baohua@kernel.org, chleroy@kernel.org, david@kernel.org, dev.jain@arm.com, jiangwen6@xiaomi.com, leo.yan@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, rppt@kernel.org, ryan.roberts@arm.com Subject: Re: [PATCH v10 05/10] arm64/vmalloc: allow arch_vmap_pte_range_map_size() to batch multiple CONT_PTE Message-ID: References: <20261002090947.869220-1-jiangwen6@xiaomi.com> <20261002090947.869220-6-jiangwen6@xiaomi.com> X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261002090947.869220-6-jiangwen6@xiaomi.com> On Fri, Oct 02, 2026 at 05:09:42PM +0800, Wen Jiang wrote: > From: "Barry Song (Xiaomi)" > > Allow arch_vmap_pte_range_map_size to batch across multiple CONT_PTE > blocks, reducing both PTE setup and TLB flush iterations. > > Previously the function returned a single CONT_PTE_SIZE for an aligned > range, so the caller mapped one CONT_PTE block per iteration. Now, for a > CONT_PTE_SIZE-aligned range, it returns the largest CONT_PTE-aligned size > that fits within both the remaining range and the caller's max_page_shift, > so a single pte_set_huge() call installs several CONT_PTE blocks at once. > > Signed-off-by: Barry Song (Xiaomi) > Signed-off-by: Wen Jiang > Tested-by: Xueyuan Chen > Tested-by: Leo Yan > --- > arch/arm64/include/asm/vmalloc.h | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/include/asm/vmalloc.h b/arch/arm64/include/asm/vmalloc.h > index 4ec1acd3c1b34..c29704a19e276 100644 > --- a/arch/arm64/include/asm/vmalloc.h > +++ b/arch/arm64/include/asm/vmalloc.h > @@ -23,10 +23,12 @@ static inline unsigned long arch_vmap_pte_range_map_size(unsigned long addr, > unsigned long end, u64 pfn, > unsigned int max_page_shift) > { > + unsigned long size; > + > /* > - * If the block is at least CONT_PTE_SIZE in size, and is naturally > - * aligned in both virtual and physical space, then we can pte-map the > - * block using the PTE_CONT bit for more efficient use of the TLB. > + * If the range is at least CONT_PTE_SIZE and naturally aligned in both > + * virtual and physical space, return the largest CONT_PTE-aligned size > + * that fits, for more efficient use of the TLB. > */ > if (max_page_shift < CONT_PTE_SHIFT) > return PAGE_SIZE; > @@ -40,7 +42,9 @@ static inline unsigned long arch_vmap_pte_range_map_size(unsigned long addr, > if (!IS_ALIGNED(PFN_PHYS(pfn), CONT_PTE_SIZE)) > return PAGE_SIZE; > > - return CONT_PTE_SIZE; > + size = min(end - addr, 1UL << max_page_shift); > + size = round_down(size, CONT_PTE_SIZE); > + return size; > } > > #define arch_vmap_pte_range_unmap_size arch_vmap_pte_range_unmap_size > -- > 2.34.1 > This is arch/arm64 code. Can you, Jain or Ryan from ARM folk review this change? Thank you! -- Uladzislau Rezki