Morris,
A long time ago, I did this for a 405 and it involves much more than just changing the page shift.
From my memory, I will give you what I think you have to do.
1)you must go into tlb handling code and change it. That is in the
header file 44x.S i beleive.
2)You have to change the pte directory sizes
3)You have to chage the linker script.
4)You have to change the size of the zero page.
5)you have to chage dcache flush routines, to cover the new page size.
You have to find where 4096/4095 is hard coded as the page size and change it.
This is no small job, and what you come up with will be very unsupported.
I beleive If you pin the kerel TLB you might get
the performance you need and this should be in the kernel config scripts.
Good luck,
Chip
On 5/1/06, moris dong <
moris_dong@hotmail.com> wrote:Friends,
My PPC440 (32bit) MMU supports multiple page sizes.
For the default 4K pages, my 2.6.11 kernel compiles and boots just fine.
I want to re-build it with large pages, to improve my application
performance.
I tried modifying PAGE_SHIFT in "page.h" to 13 (8K pages) and re-build my
kernel.
Compilation worked out fine, but my kernel does NOT boot, nor it prints
anything to the console.
Has anyone successfully compiled & booted a 2.6 kernel with pages larger
than 4K ?
What am I doing wrong ?
Thanks a lot.
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