Re: [powerpc/nmi: RFC 2/2] Keep interrupts enabled even on soft disable

[Balbir Singh <bsingharora@gmail.com>]

On 14/12/16 02:27, Benjamin Herrenschmidt wrote:
> On Tue, 2016-12-13 at 16:36 +1100, Balbir Singh wrote:
>> Yep, although the code works for PPC_XICS only which is good for now.
>> When we do XIVE, we can add more bits
> 
> We may want to do XIVE differently, dunno. On XIVE we can just poke the
> processor priority with a single MMIO store, so we don't actually need
> to "fetch" the interrupt and we can continue doing separate priorities.
> 

It would be good to have it be uniform, where the CPPR can be set to
the level of the current IRQ being processed (as seen from the controller)
but not yet finished via EOI. I've not looked at the CPPR/Context/Queue/Ring
details of the XIVE. But I'll let you provide the expertise on IRQ
handling

> Note that raising the priority would work on XICS in *theory* as well
> but HW bugs get in the way if we do that.
> 

Yep, I am not using the MFRR. Right now, I notice the CPPR is set to the
priority of the acked interrupt when we do a read of XIRR. Which works
well when we have just one priority at the moment.

> We also need to make sure you either adjust MPIC and all other PICs
> potentially used on ppc64 to do this "only one priority" thing or you
> disable that new mechanism on all those PICs.
> 

I was planning to skipping other IRQ chips for now and support just
XICS/XIVE with BOOK3S and PPC64. But we can discuss this.

> That's why I mentioned opt-in. Maybe make it conditional on a global
> boolean that gets enabled by the PIC itself, or make it an enum
> 
> enum lazy_irq_masking_mode {
> 	lazy_irq_mask_ee,	/* Use CPU EE bit (default) */
> 	lazy_irq_mask_fetch,	/* Fetch the interrupt and stash it away */
> 	lazy_irq_mask_prio	/* Change processor priority */
> };
> 
> For the latter we'd need a ppc_md. hook to do the priority change
> which xive (and potentially others like MPIC) could use.

We have set_cpu_priority for XICS, which sets the base_priority
only for the CPPR at the moment. It can be extended

Thanks for the comments,
Balbir