Re: [PATCH v10 3/8] PCI: dwc: Advertise dynamic inbound mapping support

[Christian Bruel <christian.bruel@foss.st.com>]

Hello,

While testing after this series, I encountered regressions on the 
STM32MP2, which I am unsure how to fix. The failures depend on the order 
in which the tests are run.

The STM32 ATU has 4 inbound entries. After enumeration, the first 4 ATU 
entries are allocated within ib_window_map.

On the first run of ./pci_endpoint_test -v BAR3(for example), 
SUBRRANGE_SETUP calls dw_pcie_ep_ib_atu_addr(), which frees only one ATU 
entry (BAR3), because we were in the bar_to_atu case, for the first 
submap but fails to allocate the second submap. So the test FAILs.

On the second run with a different BAR, SUBRRANGE_SETUP test calls 
dw_pcie_ep_ib_atu_addr() again, freeing the required ATU entry (BAR1) 
and successfully using the second ATU entry (3), which was left 
unallocated by the first test. then now the test PASSes

Therefore, the first invocation of ./pci_endpoint_test on any BAR always 
fails. Other invocations are fine because the first one has left the 
missing necessary ATU entry free. Whatever initial BAR number is used

I am unsure how to fix this. Always freeing all BARs before calling 
set_bar() in the epf-test seems overkill, but safe.
I am also considering modifying dw_pcie_ep_clear_ib_maps() to clear N 
num_submap entries even if ib_atu_indexes was not used yet, since only 
the full BAR is used during the first invocation from bar_to_atu. But 
the question is which ATU entry to select ? BAR+1 ?. This seems empirical.

I am not bothered by test failures due to an insufficient number of BARs 
(this is already the case for BAR5,6), but the fact that the failures 
depend on the test order is frustrating and show a regression.

But I'm not satisfied with either of the 2 possible fixes mentioned above.

Do you have any other thought ?

thank you

Christian