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Thu, 09 Jul 2026 06:10:51 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (smtpav05.fra02v.mail.ibm.com [10.20.54.104]) by smtprelay02.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 6696Al9546268674 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 9 Jul 2026 06:10:47 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 61A2D2004B; Thu, 9 Jul 2026 06:10:47 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6E2D020040; Thu, 9 Jul 2026 06:10:45 +0000 (GMT) Received: from [9.123.10.251] (unknown [9.123.10.251]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 9 Jul 2026 06:10:45 +0000 (GMT) Message-ID: Date: Thu, 9 Jul 2026 11:40:44 +0530 X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] powerpc/64s: Clarify copy_and_flush() cache sync loop comment From: Nikhil Kumar Singh To: Mukesh Kumar Chaurasiya Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, chleroy@kernel.org, adityag@linux.ibm.com, mahesh@linux.ibm.com References: <20260701182756.273019-1-nikhilks@linux.ibm.com> <20260706082708.43918-1-nikhilks@linux.ibm.com> <86bee101-6bd4-45a6-a633-34f2a52d5ace@linux.ibm.com> Content-Language: en-US In-Reply-To: <86bee101-6bd4-45a6-a633-34f2a52d5ace@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-ORIG-GUID: 619dzPPFpr1_wggIbbbPGUS9rhUE1aIY X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA5MDA1MiBTYWx0ZWRfXw2RqKiCCxxhF M5v66A7f1y2lzgDxIuBnzoxNuWvBjevWS2BxYjXAXHHuKdStfBPqQmbM3HHvH4FcDsi3/PO9LW9 jti9AF5qMU/JrxyU+k72BF8KordTxxw= X-Authority-Analysis: v=2.4 cv=DKW/JSNb c=1 sm=1 tr=0 ts=6a4f3b6c cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=9-Dk1aLpORet4t1yA3gA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-GUID: kCA3vKp66jXUS8KJu0qz1HqejdlzvEpB X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA5MDA1MiBTYWx0ZWRfX4tBuaBrfiXBU M3jJy6X0jWFqHBqD+LevfvvxPTWpj6Ivp8yKp+rIhspRy3UHMVLDbsvLdG6/kqigDj8D2CX7+Gz QPPwbDo3Q6bwvSMlrP0KC/QdCLtiZBVdo00hyJgE3m7OSszfqd3CWoAJ08FrIIbQF06eOMwKChc I/KNSG+YXPvFlHfuD89kb2Zh3AkRLUnXHiqzBYq24mfAhGhYC9mzhtEJ1NSv2NxE3KCrToRn/3Q Wlhj0Qx6I+ftNX8M4B1gzCNXTVXnwMU6PnkS1RRi/a1b/FDQ4Hjo1tozQmR21+ZST6RATRIrHxt 8aaNpyzRTRO+glon74Rni02eadLoYuiyd0L56uSRkUX1o5unKzUQHmMMuzvDccgpeQ1/dnceTXj 5qsi4QxLVo/j3qzYQ7+y3k545qsdinudw+g2c4+OwwP22+HuosJK12NLprIqAQUQJyhHWNlIF4q VKCiVOv6SB28gWXdEug== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-08_05,2026-07-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 clxscore=1015 phishscore=0 impostorscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607090052 Hi Mukesh, Ideally, checkpatch should take care of this, I see no checkpatch errors. ``` ./scripts/checkpatch.pl v2-0001-powerpc-64s-Clarify-copy_and_flush-cache-sync-loo.patch total: 0 errors, 0 warnings, 26 lines checked v2-0001-powerpc-64s-Clarify-copy_and_flush-cache-sync-loo.patch has no obvious style problems and is ready for submission. ``` Thanks ~ Nikhil On 07/07/26 12:48, Nikhil Kumar Singh wrote: > Hi Mukesh, > > Thanks for reviewing the patch and for the suggestion. > I'd prefer to keep the current alignment as I find it a bit more > readable. > > Thanks, > ~ Nikhil > > On 07/07/26 11:08, Mukesh Kumar Chaurasiya wrote: >> On Mon, Jul 06, 2026 at 01:57:08PM +0530, Nikhil Kumar Singh wrote: >>> The value loaded into r0 in copy_and_flush() represents the number of >>> 8-byte words processed between cache synchronization operations. >>> >>> The existing comment refers to cache line size, which can make it >>> appear >>> that the value is a cache line size in bytes rather than a loop count. >>> Clarify the comment to explain that the loop processes 8 words (64 >>> bytes) >>> per cache synchronization iteration, and that increasing the value >>> would >>> skip cache maintenance for intermediate cache lines. >>> >>> This is a comment-only change with no functional impact. >>> >>> Signed-off-by: Nikhil Kumar Singh >>> --- >>>   arch/powerpc/kernel/head_64.S | 20 ++++++++++++-------- >>>   1 file changed, 12 insertions(+), 8 deletions(-) >>> >>> diff --git a/arch/powerpc/kernel/head_64.S >>> b/arch/powerpc/kernel/head_64.S >>> index 63432a33ec49..a54f6f979173 100644 >>> --- a/arch/powerpc/kernel/head_64.S >>> +++ b/arch/powerpc/kernel/head_64.S >>> @@ -713,14 +713,18 @@ p_end: .8byte _end - copy_to_here >>>   _GLOBAL(copy_and_flush) >>>       addi    r5,r5,-8 >>>       addi    r6,r6,-8 >>> -4:    li    r0,8            /* Use the smallest common    */ >>> -                    /* denominator cache line    */ >>> -                    /* size.  This results in    */ >>> -                    /* extra cache line flushes    */ >>> -                    /* but operation is correct.    */ >>> -                    /* Can't get cache line size    */ >>> -                    /* from NACA as it is being    */ >>> -                    /* moved too.            */ >>> +4:    li    r0,8            /* r0 is the number of 8-byte words    */ >>> +                    /* to copy per cache sync iteration. */ >>> +                    /* 8 words * 8 bytes = 64 bytes. 64B is    */ >>> +                    /* the current default cache line size.    */ >>> +                    /* This is a loop count, not a byte    */ >>> +                    /* count. Increasing it may skip    */ >>> +                    /* dcbst/icbi for lines in between and */ >>> +                    /* leave stale instructions in icache. */ >>> +                    /* This results in extra cache line    */ >>> +                    /* flushes but operation is correct. */ >>> +                    /* Can't get cache line size from NACA */ >>> +                    /* as it is being moved too.        */ >> The comment looks fine. But the alignement of the comment is still >> different from earlier. Keep the alignment same as earlier, it looks a >> little nicer. >> >> Regards, >> Mukesh >>>         mtctr    r0            /* put # words/line in ctr    */ >>>   3:    addi    r6,r6,8            /* copy a cache line */ >>> -- >>> 2.43.5 >>>