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Thu, 17 Jul 2025 20:58:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGpJu0g9KYlPsWpo+xmLRTgKz+e8QQUO94ua3L9oR8C4BqJw408SODGzFFKZ0NCX4WD20R5fw== X-Received: by 2002:a17:902:f68a:b0:234:ba75:836 with SMTP id d9443c01a7336-23e25693676mr111435915ad.7.1752811093906; Thu, 17 Jul 2025 20:58:13 -0700 (PDT) Received: from [192.168.29.92] ([49.43.226.29]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23e3b6ef9aesm4165815ad.211.2025.07.17.20.58.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Jul 2025 20:58:13 -0700 (PDT) Message-ID: Date: Fri, 18 Jul 2025 09:28:06 +0530 X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 0/4] PCI: Add support for resetting the Root Ports in a platform specific way To: manivannan.sadhasivam@oss.qualcomm.com, Bjorn Helgaas , Mahesh J Salgaonkar , Oliver O'Halloran , Will Deacon , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Heiko Stuebner , Philipp Zabel Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-rockchip@lists.infradead.org, Niklas Cassel , Wilfred Mallawa , Lukas Wunner References: <20250715-pci-port-reset-v6-0-6f9cce94e7bb@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20250715-pci-port-reset-v6-0-6f9cce94e7bb@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE4MDAyOCBTYWx0ZWRfXzBB3/6WerdRG phBdXDIoPrbDFu4rebCx81PP5Zh+Okou7cXZ4YaVSceFaM9cai9t5S7c4LBtjmSzQKhBJsOcWly rHpbkWARYFiyzBxmP/vuUBAia7pDlOyLohoOpE5UXQMtKs1Ar+X76OQJ9iyN5zEtV43ovarNNgD EEv/fzIugO6GNLvwO/uHFqhF+qBLGL3jp2hn2TNi0US9FKRmyxs82kpbMyvilfKygnIbX6LbiWL 1pZRxqfCVoI5dinRpqEVDUCTJJEHce1GhKpPAPNB5bQ8Jq4B6uDzek7lk4xYIjGnUDbFJchmCad zm+EAxfqCIdxgMUz5DJ4+Tx/KbUlh0nJAuwYSEsvzHGpvoIQ46liebpUdaBIbW6HC3ww9Zi6Vnc fsZVzj/Jaq8/uXmkW+zDqaqP47g9mOt3x/xjrc+4VLqWFOnslstx9+J+hDcGhs5xr04BqAsu X-Proofpoint-GUID: hWKCzuCgJEO06d7lTfqohkB0956kKXsg X-Proofpoint-ORIG-GUID: hWKCzuCgJEO06d7lTfqohkB0956kKXsg X-Authority-Analysis: v=2.4 cv=Y+r4sgeN c=1 sm=1 tr=0 ts=6879c659 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=lM2dtDSGyl0QT0dfkTfTzg==:17 a=lJ8DZ0MjVbnDIa4D:21 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=ImqNvw3yTObJCdT6Mg8A:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-18_01,2025-07-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 phishscore=0 malwarescore=0 priorityscore=1501 adultscore=0 impostorscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507180028 On 7/15/2025 7:51 PM, Manivannan Sadhasivam via B4 Relay wrote: > Hi, > > Currently, in the event of AER/DPC, PCI core will try to reset the slot (Root > Port) and its subordinate devices by invoking bridge control reset and FLR. But > in some cases like AER Fatal error, it might be necessary to reset the Root > Ports using the PCI host bridge drivers in a platform specific way (as indicated > by the TODO in the pcie_do_recovery() function in drivers/pci/pcie/err.c). > Otherwise, the PCI link won't be recovered successfully. > > So this series adds a new callback 'pci_host_bridge::reset_root_port' for the > host bridge drivers to reset the Root Port when a fatal error happens. > > Also, this series allows the host bridge drivers to handle PCI link down event > by resetting the Root Ports and recovering the bus. This is accomplished by the > help of the new 'pci_host_handle_link_down()' API. Host bridge drivers are > expected to call this API (preferrably from a threaded IRQ handler) with > relevant Root Port 'pci_dev' when a link down event is detected for the port. > The API will reuse the pcie_do_recovery() function to recover the link if AER > support is enabled, otherwise it will directly call the reset_root_port() > callback of the host bridge driver (if exists). > > For reference, I've modified the pcie-qcom driver to call > pci_host_handle_link_down() API with Root Port 'pci_dev' after receiving the > LINK_DOWN global_irq event and populated 'pci_host_bridge::reset_root_port()' > callback to reset the Root Port. Since the Qcom PCIe controllers support only > a single Root Port (slot) per controller instance, the API is going to be > invoked only once. For multi Root Port controllers, the controller driver is > expected to detect the Root Port that received the link down event and call > the pci_host_handle_link_down() API with 'pci_dev' of that Root Port. > > Testing > ------- > > I've lost access to my test setup now. So Krishna (Cced) will help with testing > on the Qcom platform and Wilfred or Niklas should be able to test it on Rockchip > platform. For the moment, this series is compile tested only. Tested on QCOM platform rb3gen2. > > Changes in v6: > - Incorporated the patch: https://lore.kernel.org/all/20250524185304.26698-2-manivannan.sadhasivam@linaro.org/ > - Link to v5: https://lore.kernel.org/r/20250715-pci-port-reset-v5-0-26a5d278db40@oss.qualcomm.com > > Changes in v5: > * Reworked the pci_host_handle_link_down() to accept Root Port instead of > resetting all Root Ports in the event of link down. > * Renamed 'reset_slot' to 'reset_root_port' to avoid confusion as both terms > were used interchangibly and the series is intended to reset Root Port only. > * Added the Rockchip driver change to this series. > * Dropped the applied patches and review/tested tags due to rework. > * Rebased on top of v6.16-rc1. > > Changes in v4: > - Handled link down first in the irq handler > - Updated ICC & OPP bandwidth after link up in reset_slot() callback > - Link to v3: https://lore.kernel.org/r/20250417-pcie-reset-slot-v3-0-59a10811c962@linaro.org > > Changes in v3: > - Made the pci-host-common driver as a common library for host controller > drivers > - Moved the reset slot code to pci-host-common library > - Link to v2: https://lore.kernel.org/r/20250416-pcie-reset-slot-v2-0-efe76b278c10@linaro.org > > Changes in v2: > - Moved calling reset_slot() callback from pcie_do_recovery() to pcibios_reset_secondary_bus() > - Link to v1: https://lore.kernel.org/r/20250404-pcie-reset-slot-v1-0-98952918bf90@linaro.org > > Signed-off-by: Manivannan Sadhasivam Tested-by: Krishna Chaitanya Chundru - Krishna Chaitanya. > --- > Manivannan Sadhasivam (3): > PCI/ERR: Add support for resetting the Root Ports in a platform specific way > PCI: host-common: Add link down handling for Root Ports > PCI: qcom: Add support for resetting the Root Port due to link down event > > Wilfred Mallawa (1): > PCI: dw-rockchip: Add support to reset Root Port upon link down event > > drivers/pci/controller/dwc/Kconfig | 2 + > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 91 ++++++++++++++++++- > drivers/pci/controller/dwc/pcie-qcom.c | 120 ++++++++++++++++++++++++-- > drivers/pci/controller/pci-host-common.c | 33 +++++++ > drivers/pci/controller/pci-host-common.h | 1 + > drivers/pci/pci.c | 21 +++++ > drivers/pci/pcie/err.c | 6 +- > include/linux/pci.h | 1 + > 8 files changed, 260 insertions(+), 15 deletions(-) > --- > base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494 > change-id: 20250715-pci-port-reset-4d9519570123 > > Best regards,