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Tue, 13 Oct 2020 12:57:06 +0000 (GMT) Received: from Madhavan.PrimaryTP (unknown [9.85.92.151]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 13 Oct 2020 12:57:06 +0000 (GMT) Subject: Re: [PATCH] powerpc/perf: fix Threshold Event CounterMultiplier width for P10 To: =?UTF-8?Q?Michal_Such=c3=a1nek?= References: <20201012103128.53243-1-maddy@linux.ibm.com> <20201012112905.GQ29778@kitsune.suse.cz> From: Madhavan Srinivasan Message-ID: Date: Tue, 13 Oct 2020 18:27:05 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <20201012112905.GQ29778@kitsune.suse.cz> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-10-13_03:2020-10-13, 2020-10-13 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 suspectscore=0 phishscore=0 impostorscore=0 clxscore=1011 spamscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 mlxscore=0 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2010130096 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: atrajeev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 10/12/20 4:59 PM, Michal Suchánek wrote: > Hello, > > On Mon, Oct 12, 2020 at 04:01:28PM +0530, Madhavan Srinivasan wrote: >> Power9 and isa v3.1 has 7bit mantissa field for Threshold Event Counter > ^^^ Shouldn't his be 3.0? My bad, What I meant was Power9, ISA v3.0 and ISA v3.1 define a 7 bit mantissa field for Threshold Event Counter Multiplier(TECM). Maddy > >> Multiplier (TECM). TECM is part of Monitor Mode Control Register A (MMCRA). >> This field along with Threshold Event Counter Exponent (TECE) is used to >> get threshould counter value. In Power10, the width of TECM field is >> increase to 8bits. Patch fixes the current code to modify the MMCRA[TECM] >> extraction macro to handling this changes. >> >> Fixes: 170a315f41c64 ('powerpc/perf: Support to export MMCRA[TEC*] field to userspace') >> Signed-off-by: Madhavan Srinivasan >> --- >> arch/powerpc/perf/isa207-common.c | 3 +++ >> arch/powerpc/perf/isa207-common.h | 4 ++++ >> 2 files changed, 7 insertions(+) >> >> diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c >> index 964437adec18..5fe129f02290 100644 >> --- a/arch/powerpc/perf/isa207-common.c >> +++ b/arch/powerpc/perf/isa207-common.c >> @@ -247,6 +247,9 @@ void isa207_get_mem_weight(u64 *weight) >> u64 sier = mfspr(SPRN_SIER); >> u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; >> >> + if (cpu_has_feature(CPU_FTR_ARCH_31)) >> + mantissa = P10_MMCRA_THR_CTR_MANT(mmcra); >> + >> if (val == 0 || val == 7) >> *weight = 0; >> else >> diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h >> index 044de65e96b9..71380e854f48 100644 >> --- a/arch/powerpc/perf/isa207-common.h >> +++ b/arch/powerpc/perf/isa207-common.h >> @@ -219,6 +219,10 @@ >> #define MMCRA_THR_CTR_EXP(v) (((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\ >> MMCRA_THR_CTR_EXP_MASK) >> >> +#define P10_MMCRA_THR_CTR_MANT_MASK 0xFFul >> +#define P10_MMCRA_THR_CTR_MANT(v) (((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\ >> + P10_MMCRA_THR_CTR_MANT_MASK) >> + >> /* MMCRA Threshold Compare bit constant for power9 */ >> #define p9_MMCRA_THR_CMP_SHIFT 45 >> >> -- >> 2.26.2 >>