/*
 * Cyrus 5040 Device Tree Source, based on p5040ds.dts
 *
 * Copyright 2020 Darren Stevens
 *
 * p5040ds.dts Copyright 2012 - 2015 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * This software is provided by Freescale Semiconductor "as is" and any
 * express or implied warranties, including, but not limited to, the implied
 * warranties of merchantability and fitness for a particular purpose are
 * disclaimed. In no event shall Freescale Semiconductor be liable for any
 * direct, indirect, incidental, special, exemplary, or consequential damages
 * (including, but not limited to, procurement of substitute goods or services;
 * loss of use, data, or profits; or business interruption) however caused and
 * on any theory of liability, whether in contract, strict liability, or tort
 * (including negligence or otherwise) arising in any way out of the use of this
 * software, even if advised of the possibility of such damage.
 */

/include/ "p5040si-pre.dtsi"

/ {
	model = "varisys,CYRUS5040";
	compatible = "varisys,CYRUS";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&mpic>;

	aliases{
		ethernet0 = &enet4;
		ethernet1 = &enet10;
	};

	memory {
		device_type = "memory";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		bman_fbpr: bman-fbpr {
			size = <0 0x1000000>;
			alignment = <0 0x1000000>;
		};
		qman_fqd: qman-fqd {
			size = <0 0x400000>;
			alignment = <0 0x400000>;
		};
		qman_pfdr: qman-pfdr {
			size = <0 0x2000000>;
			alignment = <0 0x2000000>;
		};
	};

	dcsr: dcsr@f00000000 {
		ranges = <0x00000000 0xf 0x00000000 0x01008000>;
	};

	bportals: bman-portals@ff4000000 {
		ranges = <0x0 0xf 0xf4000000 0x200000>;
	};

	qportals: qman-portals@ff4200000 {
		ranges = <0x0 0xf 0xf4200000 0x200000>;
	};

	soc: soc@ffe000000 {
		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
		reg = <0xf 0xfe000000 0 0x00001000>;
		spi@110000 {
		};

		i2c@118100 {
		};

		i2c@119100 {
			rtc@6f {
				compatible = "microchip,mcp7941x";
				reg = <0x6f>;
			};
		};

		gpio-poweroff {
			compatible = "gpio-poweroff";
			gpios = <&gpio0 3 1>;
		};

		gpio-restart {
			compatible = "gpio-restart";
			gpios = <&gpio0 2 1>;
		};

		leds {
			compatible = "gpio-leds";
			hdd {
				label = "Disk activity";
				gpios = <&gpio0 5 0>;
				linux,default-trigger = "disk-activity";
			};
		};

		fman@400000 {
			mdio@e1120 {
				phy3: ethernet-phy@3 {
					reg = <0x3>;
				};

				phy7: ethernet-phy@7 {
					reg = <0x7>;
				};
			};

			ethernet@e0000 {
				status = "disabled";
			};

			ethernet@e2000 {
				status = "disabled";
			};

			ethernet@e4000 {
				status = "disabled";
			};

			ethernet@e6000 {
				status = "disabled";
			};

			ethernet@e8000 {
				phy-handle = <&phy3>;
				phy-connection-type = "rgmii";
			};

		};

		fman@500000 {
			ethernet@e0000 {
				status = "disabled";
			};

			ethernet@e2000 {
				status = "disabled";
			};

			ethernet@e4000 {
				status = "disabled";
			};

			ethernet@e6000 {
				status = "disabled";
			};

			ethernet@e8000 {
				phy-handle = <&phy7>;
				phy-connection-type = "rgmii";
			};

		};

	};

	lbc: localbus@ffe124000 {
		reg = <0xf 0xfe124000 0 0x1000>;
		ranges = <0 0 0xf 0xe8000000 0x08000000
			  2 0 0xf 0xffa00000 0x00040000
			  3 0 0xf 0xffdf0000 0x00008000>;

	};

	pci0: pcie@ffe200000 {
		reg = <0xf 0xfe200000 0 0x1000>;
		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x20000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};

	pci1: pcie@ffe201000 {
		reg = <0xf 0xfe201000 0 0x1000>;
		ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x20000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};

	pci2: pcie@ffe202000 {
		reg = <0xf 0xfe202000 0 0x1000>;
		ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x20000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};
};

/include/ "p5040si-post.dtsi"