Re: [PATCH, RESEND, 2/3] selftests/powerpc: enable performance alerts when freezing counters on cycles_with_freeze_test selftest

[Rashmica Gupta <rashmica.g@gmail.com>]

On Wed, 2020-04-08 at 19:35 -0300, Desnes A. Nunes do Rosario wrote:
> From: Gustavo Romero <gromero@linux.ibm.com>
> 
> When disabling freezing counters by setting MMCR0 FC bit to 0, the
> MMCR0
> PMAE bit must also be enabled if a Performance Monitor Alert (and the
> cor-
> responding Performance Monitor Interrupt) is still desired to be
> received
> when an enabled condition or event occurs.
> 
> This is the case of the cycles_with_freeze_test selftest, since the
> test
> disables the MMCR0 PMAE due to the usage of PMU to trigger EBBs. This
> can
> make the test loop up to the point of being killed by the test
> harness
> timeout (2500 ms), since no other ebb event will happen because the
> MMCR0
> PMAE bit is disabled, and thus, no more increments to ebb_count
> occur.
> 
> Fixes: 3752e453f6bafd7 ("selftests/powerpc: Add tests of PMU EBBs")
> Signed-off-by: Gustavo Romero <gromero@linux.ibm.com>
> [desnesn: Only set MMCR0_PMAE when disabling MMCR0_FC, reflow
> comment]
> Signed-off-by: Desnes A. Nunes do Rosario <desnesn@linux.ibm.com>

Reviewed and Tested-by: Rashmica Gupta <rashmica.g@gmail.com>

> ---
>  .../testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c | 2
> +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git
> a/tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c
> b/tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c
> index 0f2089f6f82c..d368199144fb 100644
> ---
> a/tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c
> +++
> b/tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c
> @@ -81,7 +81,7 @@ int cycles_with_freeze(void)
>  	{
>  		counters_frozen = false;
>  		mb();
> -		mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~MMCR0_FC);
> +		mtspr(SPRN_MMCR0, (mfspr(SPRN_MMCR0) & ~MMCR0_FC) |
> MMCR0_PMAE);
>  
>  		FAIL_IF(core_busy_loop());
>