* Serial console not working on EP8343M
@ 2007-03-13 3:05 Ed Swierk
2007-03-13 14:57 ` Kumar Gala
0 siblings, 1 reply; 6+ messages in thread
From: Ed Swierk @ 2007-03-13 3:05 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 870 bytes --]
I'm having trouble getting the serial console to work on an EP8343M
board when using U-Boot 1.2.0 to start Linux 2.6.20.1. I'm using arch
powerpc and platform MPC834x_SYS (which is perhaps wishful thinking,
as my board is different, although it should at least have the same
serial port configuration).
The symptoms are exactly the same as those in
http://ozlabs.org/pipermail/linuxppc-embedded/2006-September/024457.html:
the console stops working after the call to console_init(). The
suggested solution was to ensure that U-Boot is setting
timebase-frequency, bus-frequency and clock-frequency and passing
those properties to the kernel, and this does indeed seem to be
happening in my case.
I've attached the output from U-Boot (including a dump of the flat
device tree), as well as my kernel config and U-Boot board settings.
Any help would be appreciated.
--Ed
[-- Attachment #2: u-boot.out --]
[-- Type: application/octet-stream, Size: 16856 bytes --]
## Booting image at 00200000 ...
Image Name: Linux-2.6.20.1-ArosKernel-eng-15
Created: 2007-03-12 23:14:23 UTC
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 1096872 Bytes = 1 MB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
Booting using flat device tree at 0xa00000
recieved oftree
{
model = "EP8343M";
compatible = "EP8343M";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#cpus = <1>;
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8343@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>;
i-cache-line-size = <20>;
d-cache-size = <8000>;
i-cache-size = <8000>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
32-bit;
};
};
memory {
device_type = "memory";
reg = <67>;
};
soc8343@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = [00 00 00 00 e0 00 00 00 00 10 00 00];
reg = <67>;
bus-frequency = <0>;
wdt@200 {
device_type = "watchdog";
compatible = "mpc83xx_wdt";
reg = <67>;
};
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";
reg = <67>;
interrupts = <73>;
interrupt-parent = <700>;
dfsrr;
};
i2c@3100 {
device_type = "i2c";
compatible = "fsl-i2c";
reg = <67>;
interrupts = <73>;
interrupt-parent = <700>;
dfsrr;
};
spi@7000 {
device_type = "spi";
compatible = "mpc83xx_spi";
reg = <67>;
interrupts = <73>;
interrupt-parent = <700>;
mode = <0>;
};
usb@22000 {
device_type = "usb";
compatible = "fsl-usb2-mph";
reg = <67>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <700>;
interrupts = <73>;
phy_type = "ulpi";
port1;
};
usb@23000 {
device_type = "usb";
compatible = "fsl-usb2-dr";
reg = <67>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <700>;
interrupts = <73>;
phy_type = "ulpi";
};
mdio@24520 {
device_type = "mdio";
compatible = "gianfar";
reg = <67>;
#address-cells = <1>;
#size-cells = <0>;
linux,phandle = <24520>;
ethernet-phy@0 {
linux,phandle = <2452000>;
interrupt-parent = <700>;
interrupts = <73>;
reg = <0>;
device_type = "ethernet-phy";
};
ethernet-phy@1 {
linux,phandle = <2452001>;
interrupt-parent = <700>;
interrupts = <73>;
reg = <1>;
device_type = "ethernet-phy";
};
};
ethernet@24000 {
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <67>;
address = [00 00 00 00 00 00];
local-mac-address = [00 00 00 00 00 00];
interrupts = [00 00 00 20 00 00 00 08 00 00 00 21 00 00 00 08 00 00 00 22 00 00 00 08];
interrupt-parent = <700>;
phy-handle = <2452000>;
};
ethernet@25000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <67>;
address = [00 00 00 00 00 00];
local-mac-address = [00 00 00 00 00 00];
interrupts = [00 00 00 23 00 00 00 08 00 00 00 24 00 00 00 08 00 00 00 25 00 00 00 08];
interrupt-parent = <700>;
phy-handle = <2452001>;
};
serial@4500 {
device_type = "serial";
compatible = "ns16550";
reg = <67>;
clock-frequency = <0>;
interrupts = <73>;
interrupt-parent = <700>;
};
serial@4600 {
device_type = "serial";
compatible = "ns16550";
reg = <67>;
clock-frequency = <0>;
interrupts = <73>;
interrupt-parent = <700>;
};
pci@8500 {
interrupt-map-mask = [00 00 f8 00 00 00 00 00 00 00 00 00 00 00 00 07];
interrupt-map = [00 00 88 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 07 00 00 00 00 14 00 00 00 08 00 00 88 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 07 00 00 00 00 15 00 00 00 08 00 00 88 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 07 00 00 00 00 16 00 00 00 08 00 00 88 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 07 00 00 00 00 17 00 00 00 08 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 07 00 00 00 00 16 00 00 00 08 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 07 00 00 00 00 17 00 00 00 08 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 07 00 00 00 00 14 00 00 00 08 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 07 00 00 00 00 15 00 00 00 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 07 00 00 00 00 17 00 00 00 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 07 00 00 00 00 14 00 00 00 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 07 00 00 00 00 15 00 00 00 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 07 00 00 00 00 16 00 00 00 08 00 00 a8 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 07 00 00 00 00 14 00 00 00 08 00 00 a8 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 07 00 00 00 00 15 00 00 00 08 00 00 a8 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 07 00 00 00 00 16 00 00 00 08 00 00 a8 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 07 00 00 00 00 17 00 00 00 08 00 00 b0 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 07 00 00 00 00 17 00 00 00 08 00 00 b0 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 07 00 00 00 00 14 00 00 00 08 00 00 b0 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 07 00 00 00 00 15 00 00 00 08 00 00 b0 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 07 00 00 00 00 16 00 00 00 08 00 00 b8 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 07 00 00 00 00 16 00 00 00 08 00 00 b8 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 07 00 00 00 00 17 00 00 00 08 00 00 b8 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 07 00 00 00 00 14 00 00 00 08 00 00 b8 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 07 00 00 00 00 15 00 00 00 08 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 07 00 00 00 00 15 00 00 00 08 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 07 00 00 00 00 16 00 00 00 08 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 07 00 00 00 00 17 00 00 00 08 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 07 00 00 00 00 14 00 00 00 08];
interrupt-parent = <700>;
interrupts = <73>;
bus-range = <65>;
ranges = [02 00 00 00 00 00 00 00 a0 00 00 00 a0 00 00 00 00 00 00 00 10 00 00 00 42 00 00 00 00 00 00 00 80 00 00 00 80 00 00 00 00 00 00 00 10 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 e2 00 00 00 00 00 00 00 00 10 00 00];
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <67>;
compatible = "83xx";
device_type = "pci";
};
pic@700 {
linux,phandle = <700>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <67>;
built-in;
device_type = "ipic";
};
};
};
final OF-tree
{
model = "EP8343M";
compatible = "EP8343M";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#cpus = <1>;
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8343@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>;
i-cache-line-size = <20>;
d-cache-size = <8000>;
i-cache-size = <8000>;
timebase-frequency = <3ef1480>;
bus-frequency = <fbc5200>;
clock-frequency = <179a7b00>;
32-bit;
};
};
memory {
device_type = "memory";
reg = <67>;
};
soc8343@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = [00 00 00 00 e0 00 00 00 00 10 00 00];
reg = <67>;
bus-frequency = <fbc5200>;
wdt@200 {
device_type = "watchdog";
compatible = "mpc83xx_wdt";
reg = <67>;
};
i2c@3000 {
device_type = "i2c";
compatible = "fsl-i2c";
reg = <67>;
interrupts = <73>;
interrupt-parent = <700>;
dfsrr;
};
i2c@3100 {
device_type = "i2c";
compatible = "fsl-i2c";
reg = <67>;
interrupts = <73>;
interrupt-parent = <700>;
dfsrr;
};
spi@7000 {
device_type = "spi";
compatible = "mpc83xx_spi";
reg = <67>;
interrupts = <73>;
interrupt-parent = <700>;
mode = <0>;
};
usb@22000 {
device_type = "usb";
compatible = "fsl-usb2-mph";
reg = <67>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <700>;
interrupts = <73>;
phy_type = "ulpi";
port1;
};
usb@23000 {
device_type = "usb";
compatible = "fsl-usb2-dr";
reg = <67>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <700>;
interrupts = <73>;
phy_type = "ulpi";
};
mdio@24520 {
device_type = "mdio";
compatible = "gianfar";
reg = <67>;
#address-cells = <1>;
#size-cells = <0>;
linux,phandle = <24520>;
ethernet-phy@0 {
linux,phandle = <2452000>;
interrupt-parent = <700>;
interrupts = <73>;
reg = <0>;
device_type = "ethernet-phy";
};
ethernet-phy@1 {
linux,phandle = <2452001>;
interrupt-parent = <700>;
interrupts = <73>;
reg = <1>;
device_type = "ethernet-phy";
};
};
ethernet@24000 {
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <67>;
address = [00 00 00 00 00 00];
local-mac-address = [00 04 9f ef 23 33];
interrupts = [00 00 00 20 00 00 00 08 00 00 00 21 00 00 00 08 00 00 00 22 00 00 00 08];
interrupt-parent = <700>;
phy-handle = <2452000>;
};
ethernet@25000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <67>;
address = [00 00 00 00 00 00];
local-mac-address = [00 e0 0c 00 7e 21];
interrupts = [00 00 00 23 00 00 00 08 00 00 00 24 00 00 00 08 00 00 00 25 00 00 00 08];
interrupt-parent = <700>;
phy-handle = <2452001>;
};
serial@4500 {
device_type = "serial";
compatible = "ns16550";
reg = <67>;
clock-frequency = <fbc5200>;
interrupts = <73>;
interrupt-parent = <700>;
};
serial@4600 {
device_type = "serial";
compatible = "ns16550";
reg = <67>;
clock-frequency = <fbc5200>;
interrupts = <73>;
interrupt-parent = <700>;
};
pci@8500 {
interrupt-map-mask = [00 00 f8 00 00 00 00 00 00 00 00 00 00 00 00 07];
interrupt-map = [00 00 88 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 07 00 00 00 00 14 00 00 00 08 00 00 88 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 07 00 00 00 00 15 00 00 00 08 00 00 88 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 07 00 00 00 00 16 00 00 00 08 00 00 88 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 07 00 00 00 00 17 00 00 00 08 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 07 00 00 00 00 16 00 00 00 08 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 07 00 00 00 00 17 00 00 00 08 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 07 00 00 00 00 14 00 00 00 08 00 00 90 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 07 00 00 00 00 15 00 00 00 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 07 00 00 00 00 17 00 00 00 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 07 00 00 00 00 14 00 00 00 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 07 00 00 00 00 15 00 00 00 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 07 00 00 00 00 16 00 00 00 08 00 00 a8 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 07 00 00 00 00 14 00 00 00 08 00 00 a8 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 07 00 00 00 00 15 00 00 00 08 00 00 a8 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 07 00 00 00 00 16 00 00 00 08 00 00 a8 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 07 00 00 00 00 17 00 00 00 08 00 00 b0 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 07 00 00 00 00 17 00 00 00 08 00 00 b0 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 07 00 00 00 00 14 00 00 00 08 00 00 b0 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 07 00 00 00 00 15 00 00 00 08 00 00 b0 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 07 00 00 00 00 16 00 00 00 08 00 00 b8 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 07 00 00 00 00 16 00 00 00 08 00 00 b8 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 07 00 00 00 00 17 00 00 00 08 00 00 b8 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 07 00 00 00 00 14 00 00 00 08 00 00 b8 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 07 00 00 00 00 15 00 00 00 08 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 07 00 00 00 00 15 00 00 00 08 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 07 00 00 00 00 16 00 00 00 08 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 07 00 00 00 00 17 00 00 00 08 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 07 00 00 00 00 14 00 00 00 08];
interrupt-parent = <700>;
interrupts = <73>;
bus-range = <65>;
ranges = [02 00 00 00 00 00 00 00 a0 00 00 00 a0 00 00 00 00 00 00 00 10 00 00 00 42 00 00 00 00 00 00 00 80 00 00 00 80 00 00 00 00 00 00 00 10 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 e2 00 00 00 00 00 00 00 00 10 00 00];
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <67>;
compatible = "83xx";
device_type = "pci";
};
pic@700 {
linux,phandle = <700>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <67>;
built-in;
device_type = "ipic";
};
};
chosen {
name = "chosen";
bootargs = "console=uart,io,0xe0004500 console=ttyS0 loglevel=9";
linux,platform = <600>;
linux,stdout-path = "/soc8343@e0000000/serial@4500";
};
};
Using MPC834x SYS machine description
Linux version 2.6.20.1-ArosKernel-eng-15450.2006.eswierk.3403 (eswierk@ms0.arastra.com) (gcc version 4.1.1 20070105 (Red Hat 4.1.1-51)) #1 PREEMPT Mon Mar 12 16:13:42 PDT 2007
setup_arch: bootmem
mpc834x_sys_setup_arch()
Found MPC83xx PCI host bridge at 0x00000000e0008500. Firmware bus number: 0->0
arch: exit
Zone PFN ranges:
DMA 0 -> 16384
Normal 16384 -> 16384
HighMem 16384 -> 16384
early_node_map[1] active PFN ranges
0: 0 -> 16384
Built 1 zonelists. Total pages: 16256
Kernel command line: console=uart,io,0xe0004500 console=ttyS0 loglevel=9
IPIC (128 IRQ sources) at fdefc700
PID hash table entries: 256 (order: 8, 1024 bytes)
time_init: decrementer frequency = 66.000000 MHz
time_init: processor frequency = 396.000000 MHz
[-- Attachment #3: linux.config --]
[-- Type: application/octet-stream, Size: 19515 bytes --]
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.20.1
# Mon Mar 12 17:29:35 2007
#
# CONFIG_PPC64 is not set
CONFIG_PPC32=y
CONFIG_PPC_MERGE=y
CONFIG_MMU=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_IRQ_PER_CPU=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_ARCH_HAS_ILOG2_U32=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_PPC=y
CONFIG_EARLY_PRINTK=y
CONFIG_GENERIC_NVRAM=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_PPC_OF=y
CONFIG_PPC_UDBG_16550=y
# CONFIG_GENERIC_TBSYNC is not set
CONFIG_AUDIT_ARCH=y
CONFIG_GENERIC_BUG=y
CONFIG_DEFAULT_UIMAGE=y
#
# Processor support
#
# CONFIG_CLASSIC32 is not set
# CONFIG_PPC_82xx is not set
CONFIG_PPC_83xx=y
# CONFIG_PPC_85xx is not set
# CONFIG_PPC_86xx is not set
# CONFIG_40x is not set
# CONFIG_44x is not set
# CONFIG_8xx is not set
# CONFIG_E200 is not set
CONFIG_6xx=y
CONFIG_83xx=y
CONFIG_PPC_FPU=y
# CONFIG_PPC_DCR_NATIVE is not set
# CONFIG_PPC_DCR_MMIO is not set
CONFIG_PPC_STD_MMU=y
CONFIG_PPC_STD_MMU_32=y
# CONFIG_SMP is not set
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
#
# General setup
#
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
# CONFIG_IPC_NS is not set
# CONFIG_POSIX_MQUEUE is not set
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
# CONFIG_TASKSTATS is not set
# CONFIG_UTS_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
# CONFIG_EMBEDDED is not set
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SHMEM=y
CONFIG_SLAB=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_KMOD=y
#
# Block layer
#
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
CONFIG_PPC_GEN550=y
# CONFIG_WANT_EARLY_SERIAL is not set
#
# Platform support
#
# CONFIG_MPC832x_MDS is not set
CONFIG_MPC834x_SYS=y
# CONFIG_MPC834x_ITX is not set
# CONFIG_MPC8360E_PB is not set
CONFIG_MPC834x=y
# CONFIG_MPIC is not set
#
# Kernel options
#
CONFIG_HIGHMEM=y
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_PREEMPT_BKL=y
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_MATH_EMULATION is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
CONFIG_PROC_DEVICETREE=y
# CONFIG_CMDLINE_BOOL is not set
# CONFIG_PM is not set
# CONFIG_SECCOMP is not set
CONFIG_ISA_DMA_API=y
#
# Bus options
#
CONFIG_GENERIC_ISA_DMA=y
# CONFIG_MPIC_WEIRD is not set
# CONFIG_PPC_I8259 is not set
CONFIG_PPC_INDIRECT_PCI=y
CONFIG_FSL_SOC=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
# CONFIG_PCIEPORTBUS is not set
# CONFIG_PCI_DEBUG is not set
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
#
# PCI Hotplug Support
#
# CONFIG_HOTPLUG_PCI is not set
#
# Advanced setup
#
# CONFIG_ADVANCED_OPTIONS is not set
#
# Default settings for advanced configuration options are used
#
CONFIG_HIGHMEM_START=0xfe000000
CONFIG_LOWMEM_SIZE=0x30000000
CONFIG_KERNEL_START=0xc0000000
CONFIG_TASK_SIZE=0x80000000
CONFIG_BOOT_LOAD=0x00800000
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
# CONFIG_NETDEBUG is not set
# CONFIG_PACKET is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
# CONFIG_IP_PNP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
#
# DCCP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_DCCP is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_SCTP is not set
#
# TIPC Configuration (EXPERIMENTAL)
#
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_IEEE80211 is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_SYS_HYPERVISOR is not set
#
# Connector - unified userspace <-> kernelspace linker
#
# CONFIG_CONNECTOR is not set
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=m
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SX8 is not set
# CONFIG_BLK_DEV_RAM is not set
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
#
# Misc devices
#
# CONFIG_SGI_IOC4 is not set
# CONFIG_TIFM_CORE is not set
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
# CONFIG_SCSI_TGT is not set
CONFIG_SCSI_NETLINK=y
# CONFIG_SCSI_PROC_FS is not set
#
# SCSI support type (disk, tape, CD-ROM)
#
# CONFIG_BLK_DEV_SD is not set
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=y
CONFIG_SCSI_FC_ATTRS=y
CONFIG_SCSI_ISCSI_ATTRS=y
CONFIG_SCSI_SAS_ATTRS=y
# CONFIG_SCSI_SAS_LIBSAS is not set
#
# SCSI low-level drivers
#
# CONFIG_ISCSI_TCP is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_EATA is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_FC is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_LPFC is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_DC390T is not set
# CONFIG_SCSI_NSP32 is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_SRP is not set
#
# Serial ATA (prod) and Parallel ATA (experimental) drivers
#
# CONFIG_ATA is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
# CONFIG_FUSION_SPI is not set
# CONFIG_FUSION_FC is not set
# CONFIG_FUSION_SAS is not set
#
# IEEE 1394 (FireWire) support
#
# CONFIG_IEEE1394 is not set
#
# I2O device support
#
# CONFIG_I2O is not set
#
# Macintosh device drivers
#
# CONFIG_MAC_EMUMOUSEBTN is not set
# CONFIG_WINDFARM is not set
#
# Network device support
#
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
CONFIG_TUN=m
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
#
# PHY device support
#
CONFIG_PHYLIB=y
#
# MII PHY device drivers
#
# CONFIG_MARVELL_PHY is not set
# CONFIG_DAVICOM_PHY is not set
# CONFIG_QSEMI_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_SMSC_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_FIXED_PHY is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_CASSINI is not set
# CONFIG_NET_VENDOR_3COM is not set
#
# Tulip family network device support
#
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
# CONFIG_NET_PCI is not set
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_E1000 is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_R8169 is not set
# CONFIG_SIS190 is not set
# CONFIG_SKGE is not set
# CONFIG_SKY2 is not set
# CONFIG_SK98LIN is not set
# CONFIG_TIGON3 is not set
# CONFIG_BNX2 is not set
CONFIG_GIANFAR=y
CONFIG_GFAR_NAPI=y
# CONFIG_QLA3XXX is not set
#
# Ethernet (10000 Mbit)
#
# CONFIG_CHELSIO_T1 is not set
# CONFIG_IXGB is not set
# CONFIG_S2IO is not set
# CONFIG_MYRI10GE is not set
# CONFIG_NETXEN_NIC is not set
#
# Token Ring devices
#
# CONFIG_TR is not set
#
# Wireless LAN (non-hamradio)
#
# CONFIG_NET_RADIO is not set
#
# Wan interfaces
#
# CONFIG_WAN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NET_FC is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
#
# IPMI
#
CONFIG_IPMI_HANDLER=y
# CONFIG_IPMI_PANIC_EVENT is not set
CONFIG_IPMI_DEVICE_INTERFACE=y
CONFIG_IPMI_SI=y
CONFIG_IPMI_WATCHDOG=y
CONFIG_IPMI_POWEROFF=y
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
#
# TPM devices
#
# CONFIG_TCG_TPM is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
#
# Hardware Monitoring support
#
# CONFIG_HWMON is not set
# CONFIG_HWMON_VID is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# Graphics support
#
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB is not set
# CONFIG_FB_IBM_GXT4500 is not set
#
# Console display driver support
#
CONFIG_VGA_CONSOLE=y
# CONFIG_VGACON_SOFT_SCROLLBACK is not set
CONFIG_DUMMY_CONSOLE=y
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# HID Devices
#
# CONFIG_HID is not set
#
# USB support
#
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
CONFIG_USB_ARCH_HAS_EHCI=y
# CONFIG_USB is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# MMC/SD Card support
#
# CONFIG_MMC is not set
#
# LED devices
#
# CONFIG_NEW_LEDS is not set
#
# LED drivers
#
#
# LED Triggers
#
#
# InfiniBand support
#
# CONFIG_INFINIBAND is not set
#
# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
#
#
# Real Time Clock
#
# CONFIG_RTC_CLASS is not set
#
# DMA Engine support
#
# CONFIG_DMA_ENGINE is not set
#
# DMA Clients
#
#
# DMA Devices
#
#
# Virtualization
#
#
# Userspace I/O
#
CONFIG_UIO=y
#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_INOTIFY is not set
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
# CONFIG_9P_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
CONFIG_NLS_UTF8=y
#
# Distributed Lock Manager
#
# CONFIG_DLM is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_PLIST=y
CONFIG_IOMAP_COPY=y
#
# Instrumentation Support
#
# CONFIG_PROFILING is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
CONFIG_LOG_BUF_SHIFT=15
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
# CONFIG_DEBUG_RWSEMS is not set
CONFIG_DEBUG_SPINLOCK_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_HIGHMEM=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_FORCED_INLINING is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_DEBUGGER is not set
CONFIG_BDI_SWITCH=y
# CONFIG_BOOTX_TEXT is not set
# CONFIG_SERIAL_TEXT_DEBUG is not set
# CONFIG_PPC_EARLY_DEBUG is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
[-- Attachment #4: ep8343m.h --]
[-- Type: text/x-chdr, Size: 16991 bytes --]
/* -*- Mode: C; indent-tabs-mode: t -*- */
/*
* (C) Copyright 2007 Arastra, Inc.
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* ep8349m board configuration file
*
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC83XX 1 /* MPC83XX family */
#define CONFIG_MPC834X 1 /* MPC834X family */
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_EP8343M 1 /* EP8343M board specific */
#undef CONFIG_PCI
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
#define PCI_66M
#ifdef PCI_66M
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
#else
#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
#endif
#ifndef CONFIG_SYS_CLK_FREQ
#ifdef PCI_66M
#define CONFIG_SYS_CLK_FREQ 66000000
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
#else
#define CONFIG_SYS_CLK_FREQ 33000000
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
#endif
#endif
#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK))
#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */
#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */
#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */
#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */
#define CFG_SCCR_VAL ( CFG_SCCR_INIT \
| CFG_SCCR_TSEC1CM \
| CFG_SCCR_TSEC2CM \
| CFG_SCCR_ENCCM \
| CFG_SCCR_USBCM )
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
#define CFG_IMMR 0xE0000000
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00000000 /* memtest region */
#define CFG_MEMTEST_END 0x00100000
/*
* DDR Setup
*/
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
/*
* 32-bit data path mode.
*
* Please note that using this mode for devices with the real density of 64-bit
* effectively reduces the amount of available memory due to the effect of
* wrapping around while translating address to row/columns, for example in the
* 256MB module the upper 128MB get aliased with contents of the lower
* 128MB); normally this define should be used for devices with real 32-bit
* data path.
*/
#undef CONFIG_DDR_32BIT
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
#undef CONFIG_DDR_2T_TIMING
#if defined(CONFIG_SPD_EEPROM)
/*
* Determine DDR configuration from I2C interface.
*/
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
#else
/*
* Manually set up DDR parameters
*/
#define CFG_DDR_SIZE 64 /* MB */
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_COL_BIT_9)
#define CFG_DDR_TIMING_1 0x36332321
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
#define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
#if defined(CONFIG_DDR_32BIT)
/* set burst length to 8 for 32-bit data path */
#define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */
#else
/* the default burst length is 4 - for 64-bit data path */
#define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */
#endif
#endif
/*
* FLASH on the Local Bus
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFF000000 /* start of FLASH */
#define CFG_FLASH_SIZE 16 /* flash size in MB */
/* #define CFG_FLASH_USE_BUFFER_WRITE */
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \
BR_PS_32 | /* 32 bit port size */ \
BR_V) /* valid */
#define CFG_OR0_PRELIM 0xF0000060
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x8000001B /* 256 MB window size */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MID_FLASH_JUMP 0x7F000000
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef CFG_RAMBOOT
#endif
/*
* BCSR register on local bus 32KB, 8-bit wide for ADS config reg
*/
#define CFG_BCSR 0xE2400000
#define CFG_LBLAWBAR2_PRELIM CFG_BCSR /* Access window base at BCSR base */
#define CFG_LBLAWAR2_PRELIM 0x8000001B /* Access window size 32K */
#define CFG_BR2_PRELIM (CFG_BCSR | /* BCSR base address */ \
BR_PS_16 | /* 16 bit port size */ \
BR_V) /* valid */
#define CFG_OR2_PRELIM 0xF00000F0
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xfd000000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
/*
* Local Bus LCRR and LBCR regs
* LCRR: DLL bypass, Clock divider is 4
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
#define CFG_LBC_LBCR 0x00000000
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8343@0"
#define OF_SOC "soc8343@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc8343@e0000000/serial@4500"
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
#define CFG_I2C2_OFFSET 0x3100
/* TSEC */
#define CFG_TSEC1_OFFSET 0x24000
#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
#define CFG_TSEC2_OFFSET 0x25000
#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
/* USB */
#define CFG_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCI1_MMIO_BASE 0x90000000
#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xE2000000
#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
#define CFG_PCI2_MEM_BASE 0xA0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCI2_MMIO_BASE 0xB0000000
#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE
#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */
#define CFG_PCI2_IO_BASE 0x00000000
#define CFG_PCI2_IO_PHYS 0xE2100000
#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
#if defined(CONFIG_PCI)
#define PCI_ONE_PCI1
#if defined(PCI_64BIT)
#undef PCI_ALL_PCI1
#undef PCI_TWO_PCI1
#undef PCI_ONE_PCI1
#endif
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xFIXME
#define PCI_ENET0_MEMADDR 0xFIXME
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
/*
* TSEC configuration
*/
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_GMII 1 /* MII PHY management */
#define CONFIG_MPC83XX_TSEC1 1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC83XX_TSEC2 1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC0"
#endif /* CONFIG_TSEC_ENET */
/*
* Configure on-board RTC
*/
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/*
* Environment
*/
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#if defined(CFG_RAMBOOT)
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PING \
| CFG_CMD_PCI \
| CFG_CMD_I2C \
| CFG_CMD_DATE) \
& \
~(CFG_CMD_ENV \
| CFG_CMD_LOADS))
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PING \
| CFG_CMD_I2C \
| CFG_CMD_DATE) \
& \
~(CFG_CMD_ENV \
| CFG_CMD_LOADS))
#endif
#else
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PCI \
| CFG_CMD_PING \
| CFG_CMD_I2C \
| CFG_CMD_DATE \
)
#else
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PING \
| CFG_CMD_I2C \
| CFG_CMD_MII \
| CFG_CMD_DATE \
)
#endif
#endif
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
#define CFG_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_1X1 |\
HRCWL_CSB_TO_CLKIN_4X1 |\
HRCWL_VCO_1X2 |\
HRCWL_CORE_TO_CSB_2X1)
#if defined(PCI_64BIT)
#define CFG_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_64_BIT_PCI |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_PCI2_ARBITER_DISABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
HRCWH_TSEC2M_IN_GMII )
#else
#define CFG_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_32_BIT_PCI |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_PCI2_ARBITER_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
HRCWH_TSEC2M_IN_GMII )
#endif
/* System IO Config */
#define CFG_SICRH SICRH_TSOBI1
#define CFG_SICRL SICRL_LDP_A
#define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
/* #define CFG_HID0_FINAL (\
HID0_ENABLE_INSTRUCTION_CACHE |\
HID0_ENABLE_M_BIT |\
HID0_ENABLE_ADDRESS_BROADCAST ) */
#define CFG_HID2 HID2_HBE
/* DDR @ 0x00000000 */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
/* PCI @ 0x80000000 */
#ifdef CONFIG_PCI
#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#else
#define CFG_IBAT1L (0)
#define CFG_IBAT1U (0)
#define CFG_IBAT2L (0)
#define CFG_IBAT2U (0)
#endif
#ifdef CONFIG_MPC83XX_PCI2
#define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#else
#define CFG_IBAT3L (0)
#define CFG_IBAT3U (0)
#define CFG_IBAT4L (0)
#define CFG_IBAT4U (0)
#endif
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT7L (0)
#define CFG_IBAT7U (0)
#define CFG_DBAT0L CFG_IBAT0L
#define CFG_DBAT0U CFG_IBAT0U
#define CFG_DBAT1L CFG_IBAT1L
#define CFG_DBAT1U CFG_IBAT1U
#define CFG_DBAT2L CFG_IBAT2L
#define CFG_DBAT2U CFG_IBAT2U
#define CFG_DBAT3L CFG_IBAT3L
#define CFG_DBAT3U CFG_IBAT3U
#define CFG_DBAT4L CFG_IBAT4L
#define CFG_DBAT4U CFG_IBAT4U
#define CFG_DBAT5L CFG_IBAT5L
#define CFG_DBAT5U CFG_IBAT5U
#define CFG_DBAT6L CFG_IBAT6L
#define CFG_DBAT6U CFG_IBAT6U
#define CFG_DBAT7L CFG_IBAT7L
#define CFG_DBAT7U CFG_IBAT7U
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_ETHADDR 00:04:9f:ef:23:33
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21
#endif
#define CONFIG_IPADDR 192.168.1.253
#define CONFIG_HOSTNAME ep8343m
#define CONFIG_ROOTPATH /nfsroot/rootfs
#define CONFIG_BOOTFILE uImage
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0"
#endif /* __CONFIG_H */
[-- Attachment #5: ep8343m.c --]
[-- Type: text/x-csrc, Size: 16133 bytes --]
/*
* (C) Copyright 2007 Arastra, Inc.
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <spd.h>
#include <miiphy.h>
#include <command.h>
#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
#endif
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
int fixed_sdram(void);
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
void ddr_enable_ecc(unsigned int dram_size);
#endif
int board_early_init_f (void)
{
volatile u8* bcsr = (volatile u8*)CFG_BCSR;
/*drive TRST low*/
bcsr[0x8] = 0xa0;
/* Enable flash write */
bcsr[9] &= ~0x40;
/* Enable nvram */
bcsr[9] |= 0x0c;
/* Enable eeprom write*/
bcsr[0xa] &= ~0x08;
/*enable ethernet and USB*/
bcsr[0xb] = 0xa8;
/*enable monitor*/
bcsr[0xc] |= 0x80;
/*enable PCI interrupts*/
bcsr[0xe] = 0x0c;
return 0;
}
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
long int initdram (int board_type)
{
volatile immap_t *im = (immap_t *)CFG_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
puts("Initializing\n");
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
msize = spd_sdram();
#else
msize = fixed_sdram();
#endif
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize and enable DDR ECC.
*/
ddr_enable_ecc(msize * 1024 * 1024);
#endif
puts(" DDR RAM: ");
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *)CFG_IMMR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
#ifdef CONFIG_83xxDDR_ECC
int i;
int last_i;
#endif
msize = CFG_DDR_SIZE;
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1);
ddr_size = ddr_size>>1, ddr_size_log2++) {
if (ddr_size & 1) {
return -1;
}
}
im->sysconf.ddrlaw[0].ar = 0x8000001b;
im->ddr.csbnds[0].csbnds = 0x00000008;
im->ddr.csbnds[1].csbnds = 0x00000000;
im->ddr.csbnds[2].csbnds = 0x00000000;
im->ddr.csbnds[3].csbnds = 0x00000000f;
im->ddr.cs_config[0] = CFG_DDR_CONFIG;
im->ddr.cs_config[1] = 0x00000000;
im->ddr.cs_config[2] = 0x00000000;
im->ddr.cs_config[3] = 0x00000000;
im->ddr.timing_cfg_1 =
2 << TIMING_CFG1_PRETOACT_SHIFT |
6 << TIMING_CFG1_ACTTOPRE_SHIFT |
2 << TIMING_CFG1_ACTTORW_SHIFT |
2 << TIMING_CFG1_CASLAT_SHIFT |
0xa << TIMING_CFG1_REFREC_SHIFT |
2 << TIMING_CFG1_WRREC_SHIFT |
2 << TIMING_CFG1_ACTTOACT_SHIFT |
1 << TIMING_CFG1_WRTORD_SHIFT;
im->ddr.timing_cfg_2 = 0x00081000;
#ifdef CONFIG_83xxDDR_ECC
im->ddr.err_int_en = 0x00000000;
im->ddr.err_disable = 0x00000009;
im->ddr.err_sbe = 0x00ff0000;
im->ddr.err_detect = 0x80000000;
im->ddr.sdram_cfg = 0x220c0000;
#else
im->ddr.sdram_cfg = 0x020c8000;
#endif
im->ddr.sdram_mode = 0x00000000;
im->ddr.sdram_mode = 0x0000 << SDRAM_MODE_ESD_SHIFT |
0x0023 << SDRAM_MODE_SD_SHIFT;
im->ddr.sdram_interval = 0x1E78 << SDRAM_INTERVAL_REFINT_SHIFT |
0x0000 << SDRAM_INTERVAL_BSTOPRE_SHIFT;
im->ddr.sdram_clk_cntl = 0x83000000;
udelay(200);
im->ddr.sdram_cfg |= 0xc0000000;
#ifdef CONFIG_83xxDDR_ECC
/*Need to zero out RAM to make ECC happy
TAKES FOREVER*/
last_i = i = (msize * 1024 * 1024) - 128;
#if 1
for(i=(msize * 1024 * 1024) - 1; i>=0; i-=128)
{
*(int*)i = 0x0;
*(int*)(i+4) = 0x0;
*(int*)(i+8) = 0x0;
*(int*)(i+12) = 0x0;
*(int*)(i+16) = 0x0;
*(int*)(i+20) = 0x0;
*(int*)(i+24) = 0x0;
*(int*)(i+28) = 0x0;
*(int*)(i+32) = 0x0;
*(int*)(i+36) = 0x0;
*(int*)(i+40) = 0x0;
*(int*)(i+44) = 0x0;
*(int*)(i+48) = 0x0;
*(int*)(i+52) = 0x0;
*(int*)(i+56) = 0x0;
*(int*)(i+60) = 0x0;
*(int*)(i+64) = 0x0;
*(int*)(i+68) = 0x0;
*(int*)(i+72) = 0x0;
*(int*)(i+76) = 0x0;
*(int*)(i+80) = 0x0;
*(int*)(i+84) = 0x0;
*(int*)(i+88) = 0x0;
*(int*)(i+92) = 0x0;
*(int*)(i+96) = 0x0;
*(int*)(i+100) = 0x0;
*(int*)(i+104) = 0x0;
*(int*)(i+108) = 0x0;
*(int*)(i+112) = 0x0;
*(int*)(i+116) = 0x0;
*(int*)(i+120) = 0x0;
*(int*)(i+124) = 0x0;
if( (last_i - i) > 0x200000)
{
last_i = i;
printf(".");
}
if(i==0) break;
}
#endif
/*Clear error count*/
im->ddr.err_sbe = 0x00ff0000;
#endif
return msize;
}
#endif/*!CFG_SPD_EEPROM*/
int checkboard (void)
{
puts("Board: Embedded Planet EP8343M\n");
return 0;
}
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
/*
* ECC user commands
*/
void ecc_print_status(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ddr83xx_t *ddr = &immap->ddr;
printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
/* Interrupts */
printf("Memory Error Interrupt Enable:\n");
printf(" Multiple-Bit Error Interrupt Enable: %d\n",
(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
printf(" Single-Bit Error Interrupt Enable: %d\n",
(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
printf(" Memory Select Error Interrupt Enable: %d\n\n",
(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
/* Error disable */
printf("Memory Error Disable:\n");
printf(" Multiple-Bit Error Disable: %d\n",
(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
printf(" Sinle-Bit Error Disable: %d\n",
(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
printf(" Memory Select Error Disable: %d\n\n",
(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
/* Error injection */
printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
ddr->data_err_inject_hi, ddr->data_err_inject_lo);
printf("Memory Data Path Error Injection Mask ECC:\n");
printf(" ECC Mirror Byte: %d\n",
(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
printf(" ECC Injection Enable: %d\n",
(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
printf(" ECC Error Injection Mask: 0x%02x\n\n",
ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
/* SBE counter/threshold */
printf("Memory Single-Bit Error Management (0..255):\n");
printf(" Single-Bit Error Threshold: %d\n",
(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
printf(" Single-Bit Error Counter: %d\n\n",
(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
/* Error detect */
printf("Memory Error Detect:\n");
printf(" Multiple Memory Errors: %d\n",
(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
printf(" Multiple-Bit Error: %d\n",
(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
printf(" Single-Bit Error: %d\n",
(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
printf(" Memory Select Error: %d\n\n",
(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
/* Capture data */
printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
ddr->capture_data_hi, ddr->capture_data_lo);
printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
ddr->capture_ecc & CAPTURE_ECC_ECE);
printf("Memory Error Attributes Capture:\n");
printf(" Data Beat Number: %d\n",
(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
printf(" Transaction Size: %d\n",
(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
printf(" Transaction Source: %d\n",
(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
printf(" Transaction Type: %d\n",
(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
printf(" Error Information Valid: %d\n\n",
ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
}
int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ddr83xx_t *ddr = &immap->ddr;
volatile u32 val;
u64 *addr, count, val64;
register u64 *i;
if (argc > 4) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if (argc == 2) {
if (strcmp(argv[1], "status") == 0) {
ecc_print_status();
return 0;
} else if (strcmp(argv[1], "captureclear") == 0) {
ddr->capture_address = 0;
ddr->capture_data_hi = 0;
ddr->capture_data_lo = 0;
ddr->capture_ecc = 0;
ddr->capture_attributes = 0;
return 0;
}
}
if (argc == 3) {
if (strcmp(argv[1], "sbecnt") == 0) {
val = simple_strtoul(argv[2], NULL, 10);
if (val > 255) {
printf("Incorrect Counter value, should be 0..255\n");
return 1;
}
val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
ddr->err_sbe = val;
return 0;
} else if (strcmp(argv[1], "sbethr") == 0) {
val = simple_strtoul(argv[2], NULL, 10);
if (val > 255) {
printf("Incorrect Counter value, should be 0..255\n");
return 1;
}
val = (val << ECC_ERROR_MAN_SBET_SHIFT);
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
ddr->err_sbe = val;
return 0;
} else if (strcmp(argv[1], "errdisable") == 0) {
val = ddr->err_disable;
if (strcmp(argv[2], "+sbe") == 0) {
val |= ECC_ERROR_DISABLE_SBED;
} else if (strcmp(argv[2], "+mbe") == 0) {
val |= ECC_ERROR_DISABLE_MBED;
} else if (strcmp(argv[2], "+mse") == 0) {
val |= ECC_ERROR_DISABLE_MSED;
} else if (strcmp(argv[2], "+all") == 0) {
val |= (ECC_ERROR_DISABLE_SBED |
ECC_ERROR_DISABLE_MBED |
ECC_ERROR_DISABLE_MSED);
} else if (strcmp(argv[2], "-sbe") == 0) {
val &= ~ECC_ERROR_DISABLE_SBED;
} else if (strcmp(argv[2], "-mbe") == 0) {
val &= ~ECC_ERROR_DISABLE_MBED;
} else if (strcmp(argv[2], "-mse") == 0) {
val &= ~ECC_ERROR_DISABLE_MSED;
} else if (strcmp(argv[2], "-all") == 0) {
val &= ~(ECC_ERROR_DISABLE_SBED |
ECC_ERROR_DISABLE_MBED |
ECC_ERROR_DISABLE_MSED);
} else {
printf("Incorrect err_disable field\n");
return 1;
}
ddr->err_disable = val;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
return 0;
} else if (strcmp(argv[1], "errdetectclr") == 0) {
val = ddr->err_detect;
if (strcmp(argv[2], "mme") == 0) {
val |= ECC_ERROR_DETECT_MME;
} else if (strcmp(argv[2], "sbe") == 0) {
val |= ECC_ERROR_DETECT_SBE;
} else if (strcmp(argv[2], "mbe") == 0) {
val |= ECC_ERROR_DETECT_MBE;
} else if (strcmp(argv[2], "mse") == 0) {
val |= ECC_ERROR_DETECT_MSE;
} else if (strcmp(argv[2], "all") == 0) {
val |= (ECC_ERROR_DETECT_MME |
ECC_ERROR_DETECT_MBE |
ECC_ERROR_DETECT_SBE |
ECC_ERROR_DETECT_MSE);
} else {
printf("Incorrect err_detect field\n");
return 1;
}
ddr->err_detect = val;
return 0;
} else if (strcmp(argv[1], "injectdatahi") == 0) {
val = simple_strtoul(argv[2], NULL, 16);
ddr->data_err_inject_hi = val;
return 0;
} else if (strcmp(argv[1], "injectdatalo") == 0) {
val = simple_strtoul(argv[2], NULL, 16);
ddr->data_err_inject_lo = val;
return 0;
} else if (strcmp(argv[1], "injectecc") == 0) {
val = simple_strtoul(argv[2], NULL, 16);
if (val > 0xff) {
printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
return 1;
}
val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
ddr->ecc_err_inject = val;
return 0;
} else if (strcmp(argv[1], "inject") == 0) {
val = ddr->ecc_err_inject;
if (strcmp(argv[2], "en") == 0)
val |= ECC_ERR_INJECT_EIEN;
else if (strcmp(argv[2], "dis") == 0)
val &= ~ECC_ERR_INJECT_EIEN;
else
printf("Incorrect command\n");
ddr->ecc_err_inject = val;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
return 0;
} else if (strcmp(argv[1], "mirror") == 0) {
val = ddr->ecc_err_inject;
if (strcmp(argv[2], "en") == 0)
val |= ECC_ERR_INJECT_EMB;
else if (strcmp(argv[2], "dis") == 0)
val &= ~ECC_ERR_INJECT_EMB;
else
printf("Incorrect command\n");
ddr->ecc_err_inject = val;
return 0;
}
}
if (argc == 4) {
if (strcmp(argv[1], "test") == 0) {
addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
count = simple_strtoul(argv[3], NULL, 16);
if ((u32)addr % 8) {
printf("Address not alligned on double word boundary\n");
return 1;
}
disable_interrupts();
icache_disable();
for (i = addr; i < addr + count; i++) {
/* enable injects */
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
/* write memory location injecting errors */
*i = 0x1122334455667788ULL;
__asm__ __volatile__ ("sync");
/* disable injects */
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
/* read data, this generates ECC error */
val64 = *i;
__asm__ __volatile__ ("sync");
/* disable errors for ECC */
ddr->err_disable |= ~ECC_ERROR_ENABLE;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
/* re-initialize memory, write the location again
* NOT injecting errors this time */
*i = 0xcafecafecafecafeULL;
__asm__ __volatile__ ("sync");
/* enable errors for ECC */
ddr->err_disable &= ECC_ERROR_ENABLE;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
}
icache_enable();
enable_interrupts();
return 0;
}
}
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
U_BOOT_CMD(
ecc, 4, 0, do_ecc,
"ecc - support for DDR ECC features\n",
"status - print out status info\n"
"ecc captureclear - clear capture regs data\n"
"ecc sbecnt <val> - set Single-Bit Error counter\n"
"ecc sbethr <val> - set Single-Bit Threshold\n"
"ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
" [-|+]sbe - Single-Bit Error\n"
" [-|+]mbe - Multiple-Bit Error\n"
" [-|+]mse - Memory Select Error\n"
" [-|+]all - all errors\n"
"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
" mme - Multiple Memory Errors\n"
" sbe - Single-Bit Error\n"
" mbe - Multiple-Bit Error\n"
" mse - Memory Select Error\n"
" all - all errors\n"
"ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
"ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
"ecc injectecc <ecc> - set ECC Error Injection Mask\n"
"ecc inject <en|dis> - enable/disable error injection\n"
"ecc mirror <en|dis> - enable/disable mirror byte\n"
"ecc test <addr> <cnt> - test mem region:\n"
" - enables injects\n"
" - writes pattern injecting errors\n"
" - disables injects\n"
" - reads pattern back, generates error\n"
" - re-inits memory"
);
#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
u32 *p;
int len;
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
p = ft_get_prop(blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
}
#endif
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Serial console not working on EP8343M
2007-03-13 3:05 Serial console not working on EP8343M Ed Swierk
@ 2007-03-13 14:57 ` Kumar Gala
2007-03-13 15:05 ` RE : " alayrac
2007-03-13 18:22 ` Ed Swierk
0 siblings, 2 replies; 6+ messages in thread
From: Kumar Gala @ 2007-03-13 14:57 UTC (permalink / raw)
To: Ed Swierk; +Cc: linuxppc-embedded
On Mar 12, 2007, at 10:05 PM, Ed Swierk wrote:
> I'm having trouble getting the serial console to work on an EP8343M
> board when using U-Boot 1.2.0 to start Linux 2.6.20.1. I'm using arch
> powerpc and platform MPC834x_SYS (which is perhaps wishful thinking,
> as my board is different, although it should at least have the same
> serial port configuration).
>
> The symptoms are exactly the same as those in
> http://ozlabs.org/pipermail/linuxppc-embedded/2006-September/
> 024457.html:
> the console stops working after the call to console_init(). The
> suggested solution was to ensure that U-Boot is setting
> timebase-frequency, bus-frequency and clock-frequency and passing
> those properties to the kernel, and this does indeed seem to be
> happening in my case.
>
> I've attached the output from U-Boot (including a dump of the flat
> device tree), as well as my kernel config and U-Boot board settings.
> Any help would be appreciated.
>
> --Ed
Have you tried make the bootargs just console=ttyS0,115200 (or
whatever your baud rate is)?
- k
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE : Serial console not working on EP8343M
2007-03-13 14:57 ` Kumar Gala
@ 2007-03-13 15:05 ` alayrac
2007-03-13 18:22 ` Ed Swierk
1 sibling, 0 replies; 6+ messages in thread
From: alayrac @ 2007-03-13 15:05 UTC (permalink / raw)
To: 'Kumar Gala', 'Ed Swierk'; +Cc: linuxppc-embedded
Hi Kumar,
I don't really know if i twill help you but I face the same problem some
times ago with Linux 2.6.17.4 and Linux 2.6.19.7.
I fixe the console error just by manually creating the node /dev/console
in the root file system to be mounted.
This device was automatically generated when I was using Linux-2.4.26.
I guess it help
Chris
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Serial console not working on EP8343M
2007-03-13 14:57 ` Kumar Gala
2007-03-13 15:05 ` RE : " alayrac
@ 2007-03-13 18:22 ` Ed Swierk
2007-03-13 18:45 ` Ed Swierk
2007-03-13 19:02 ` Ed Swierk
1 sibling, 2 replies; 6+ messages in thread
From: Ed Swierk @ 2007-03-13 18:22 UTC (permalink / raw)
To: linuxppc-embedded
On 3/13/07, Kumar Gala <galak@kernel.crashing.org> wrote:
> Have you tried make the bootargs just console=ttyS0,115200 (or
> whatever your baud rate is)?
I've tried that too. I just stepped through most of the
console_initcall sequence with gdb and it seems like everything is
getting set up properly, including irq and mmio settings for the
serial devices, but still nothing gets printed. Maybe interrupts
aren't getting routed?
I just discovered the udbg-immortal command line option, which
prevents console_init from optimistically disabling the udbg console.
Debugging this problem should be a lot easier now that I can see
console output past console_init.
--Ed
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Serial console not working on EP8343M
2007-03-13 18:22 ` Ed Swierk
@ 2007-03-13 18:45 ` Ed Swierk
2007-03-13 19:02 ` Ed Swierk
1 sibling, 0 replies; 6+ messages in thread
From: Ed Swierk @ 2007-03-13 18:45 UTC (permalink / raw)
To: linuxppc-embedded
Another thing I've discovered is that enabling CONFIG_IPMI_HANDLER is
a bad idea, as init_ipmi_si just hangs. I didn't look into why, as I
have no need for IPMI and just disabled it.
--Ed
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Serial console not working on EP8343M
2007-03-13 18:22 ` Ed Swierk
2007-03-13 18:45 ` Ed Swierk
@ 2007-03-13 19:02 ` Ed Swierk
1 sibling, 0 replies; 6+ messages in thread
From: Ed Swierk @ 2007-03-13 19:02 UTC (permalink / raw)
To: linuxppc-embedded
OK, problem solved. Once I kicked out that nasty IPMI driver,
everything works, including the serial console without udbg-immortal.
Lessons learned:
- passing "udbg-immortal loglevel=9 initcall_debug" to the kernel will
give you much more visibility into early init problems (at least on
powerpc arch circa 2.6.20)
- building U-Boot 1.2.0 with DEBUG defined in ft_build.c helps in
troubleshooting flat device tree problems
- the Abatron BDI2000 is an incredibly useful tool: source-level
debugging of U-Boot and the Linux kernel, starting at instruction zero
*swoon*
--Ed
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2007-03-14 0:28 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2007-03-13 3:05 Serial console not working on EP8343M Ed Swierk
2007-03-13 14:57 ` Kumar Gala
2007-03-13 15:05 ` RE : " alayrac
2007-03-13 18:22 ` Ed Swierk
2007-03-13 18:45 ` Ed Swierk
2007-03-13 19:02 ` Ed Swierk
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