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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id l2-20020a1709060cc200b006d3d91e88c7sm4371417ejh.214.2022.04.25.23.53.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 Apr 2022 23:53:19 -0700 (PDT) Message-ID: Date: Tue, 26 Apr 2022 08:53:18 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v2 1/2] dt-bindings: interrupt-controller: fsl, ls-extirq: convert to YAML Content-Language: en-US To: Michael Walle References: <20220425140214.32448-1-michael@walle.cc> <658851ed-33fd-8e2b-7db7-ef1ca9e31c33@linaro.org> <83b596d0570c779c61c3c37c6f512679@walle.cc> From: Krzysztof Kozlowski In-Reply-To: <83b596d0570c779c61c3c37c6f512679@walle.cc> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Marc Zyngier , linuxppc-dev@lists.ozlabs.org, Li Yang , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner , Shawn Guo , linux-arm-kernel@lists.infradead.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 25/04/2022 23:58, Michael Walle wrote: >>> + reg: >>> + maxItems: 1 >>> + description: >>> + Specifies the Interrupt Polarity Control Register (INTPCR) in >>> the >>> + SCFG or the External Interrupt Control Register (IRQCR) in the >>> ISC. >>> + >>> + interrupt-map: > > btw. > > minItems: 12 > maxItems: 12 > > Isn't working here, is that expected? The validator seem to get the > count > of the elements of one tuple wrong. > > I.e. > arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dtb: > interrupt-controller@14: interrupt-map: [[0, 0, 1, 0, 0, 4, 1, 0], [1, > 0, 1, 4, 2, 0, 1, 0], [2, 4, 3, 0, 1, 0, 3, 4], [4, 0, 1, 0, 4, 4, 5, > 0], [1, 0, 5, 4, 6, 0, 1, 0], [6, 4, 7, 0, 1, 0, 7, 4], [8, 0, 1, 0, 8, > 4, 9, 0], [1, 0, 9, 4, 10, 0, 1, 0], [10, 4, 11, 0, 1, 0, 11, 4]] is too > short Works for me (in different schema)... maybe update your dtschema? > >>> + description: Specifies the mapping from external interrupts to >>> GIC interrupts. >>> + >>> + interrupt-map-mask: >>> + items: >>> + - const: 0xffffffff >> >> This looks highly permissive mask and should be instead defined per >> variant, for example (quickly looking at DTS): >> 0x7 for ls1021 >> 0xf for ls1043a and ls1088a > > Just that I understand it correctly, the result of the AND with that > mask is then looked up in the interrupt-map (the first entry there)? Yes, the child (first) interrupt specifier. Since address-cells are 0, this will be bit-AND with [0-5]. >> You might need to correct the DTS. Some confirmation from someone with >> datasheet would be good. > > According to their datasheets they have the following number of external > IRQs: > - ls1021a has 6, > - ls1043a has 12, > - ls1046a has 12, > - ls1088a has 12, > - ls2080a has 12, > - lx2160a has 12. > > That is what I need to confirm, right? Yes. > > Is there a better way than the following snippet: > > properties: > interrupt-map-mask: true > > allOf: > - if: > properties: > compatible: > contains: > enum: > - fsl,ls1021a-extirq > then: > properties: > interrupt-map-mask: > items: > - const: 0x7 > - const: 0 > - if: > properties: > compatible: > contains: > enum: > - fsl,ls1043a-extirq > - fsl,ls1046a-extirq > - fsl,ls1088a-extirq > - fsl,ls2080a-extirq > - fsl,lx2160a-extirq > then: > properties: > interrupt-map-mask: > items: > - const: 0xf > - const: 0 > Exactly like this, looks good. Thank you. Best regards, Krzysztof