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Mon, 25 Jan 2021 04:52:22 GMT Received: from b03cxnp08028.gho.boulder.ibm.com (b03cxnp08028.gho.boulder.ibm.com [9.17.130.20]) by ppma03dal.us.ibm.com with ESMTP id 368be8q8vb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Jan 2021 04:52:22 +0000 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 10P4qK5M30999006 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 25 Jan 2021 04:52:20 GMT Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 814F67805E; Mon, 25 Jan 2021 04:52:20 +0000 (GMT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 89F117805F; Mon, 25 Jan 2021 04:52:18 +0000 (GMT) Received: from [9.199.63.224] (unknown [9.199.63.224]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP; Mon, 25 Jan 2021 04:52:18 +0000 (GMT) Subject: Re: [PATCH] lib/sstep: Fix incorrect return from analyze_instr() To: Michael Ellerman , linuxppc-dev@lists.ozlabs.org References: <161124771457.333703.14641179082577500423.stgit@thinktux.local> <87zh10pk50.fsf@mpe.ellerman.id.au> From: Ananth N Mavinakayanahalli Organization: IBM Message-ID: Date: Mon, 25 Jan 2021 10:22:17 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <87zh10pk50.fsf@mpe.ellerman.id.au> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2021-01-25_01:2021-01-22, 2021-01-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 impostorscore=0 mlxlogscore=999 malwarescore=0 lowpriorityscore=0 mlxscore=0 phishscore=0 clxscore=1015 priorityscore=1501 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2101250020 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ananth@linux.ibm.com Cc: naveen.n.rao@linux.ibm.com, ravi.bangoria@linux.ibm.com, paulus@samba.org, sandipan@linux.ibm.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 1/23/21 6:03 AM, Michael Ellerman wrote: > Ananth N Mavinakayanahalli writes: >> We currently just percolate the return value from analyze_instr() >> to the caller of emulate_step(), especially if it is a -1. >> >> For one particular case (opcode = 4) for instructions that >> aren't currently emulated, we are returning 'should not be >> single-stepped' while we should have returned 0 which says >> 'did not emulate, may have to single-step'. >> >> Signed-off-by: Ananth N Mavinakayanahalli >> Tested-by: Naveen N. Rao >> --- >> arch/powerpc/lib/sstep.c | 49 +++++++++++++++++++++++++--------------------- >> 1 file changed, 27 insertions(+), 22 deletions(-) >> >> diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c >> index 5a425a4a1d88..a3a0373843cd 100644 >> --- a/arch/powerpc/lib/sstep.c >> +++ b/arch/powerpc/lib/sstep.c >> @@ -1445,34 +1445,39 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, >> >> #ifdef __powerpc64__ >> case 4: >> - if (!cpu_has_feature(CPU_FTR_ARCH_300)) >> - return -1; >> - >> - switch (word & 0x3f) { >> - case 48: /* maddhd */ >> - asm volatile(PPC_MADDHD(%0, %1, %2, %3) : >> - "=r" (op->val) : "r" (regs->gpr[ra]), >> - "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); >> - goto compute_done; >> + /* >> + * There are very many instructions with this primary opcode >> + * introduced in the ISA as early as v2.03. However, the ones >> + * we currently emulate were all introduced with ISA 3.0 >> + */ >> + if (cpu_has_feature(CPU_FTR_ARCH_300)) { >> + switch (word & 0x3f) { >> + case 48: /* maddhd */ >> + asm volatile(PPC_MADDHD(%0, %1, %2, %3) : >> + "=r" (op->val) : "r" (regs->gpr[ra]), >> + "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); >> + goto compute_done; > > Indenting everything makes this patch harder to read, and I think makes > the resulting code harder to read too. We already have two levels of > switch here, and we're inside a ~1700 line function, so keeping things > simple is important I think. > > Doesn't this achieve the same result? > > diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c > index bf7a7d62ae8b..d631baaf1da2 100644 > --- a/arch/powerpc/lib/sstep.c > +++ b/arch/powerpc/lib/sstep.c > @@ -1443,8 +1443,10 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, > > #ifdef __powerpc64__ > case 4: > - if (!cpu_has_feature(CPU_FTR_ARCH_300)) > - return -1; > + if (!cpu_has_feature(CPU_FTR_ARCH_300)) { > + op->type = UNKNOWN; > + return 0; > + } > > switch (word & 0x3f) { > case 48: /* maddhd */ > @@ -1470,7 +1472,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, > * There are other instructions from ISA 3.0 with the same > * primary opcode which do not have emulation support yet. > */ > - return -1; > + op->type = UNKNOWN; > + return 0; > #endif > > case 7: /* mulli */ > Looks good to me. Acked-by: Ananth N Mavinakayanahalli -- Ananth