Re: [PATCH v4 20/36] powerpc: Implement the new page table range API

[Christophe Leroy <christophe.leroy@csgroup.eu>]

Le 15/03/2023 à 10:43, Christophe Leroy a écrit :
> 
> 
> Le 15/03/2023 à 06:14, Matthew Wilcox (Oracle) a écrit :
>> Add set_ptes(), update_mmu_cache_range() and flush_dcache_folio().
>> Change the PG_arch_1 (aka PG_dcache_dirty) flag from being per-page to
>> per-folio.
>>
>> Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org>
>> Cc: Michael Ellerman <mpe@ellerman.id.au>
>> Cc: Nicholas Piggin <npiggin@gmail.com>
>> Cc: Christophe Leroy <christophe.leroy@csgroup.eu>
>> Cc: linuxppc-dev@lists.ozlabs.org
>> ---

>> @@ -203,7 +203,14 @@ void set_pte_at(struct mm_struct *mm, unsigned 
>> long addr, pte_t *ptep,
>>       pte = set_pte_filter(pte);
>>       /* Perform the setting of the PTE */
>> -    __set_pte_at(mm, addr, ptep, pte, 0);
>> +    for (;;) {
>> +        __set_pte_at(mm, addr, ptep, pte, 0);
>> +        if (--nr == 0)
>> +            break;
>> +        ptep++;
>> +        pte = __pte(pte_val(pte) + PAGE_SIZE);
> 
> I don't like that math too much, but I have no better idea at the moment.
> 
> Maybe set_ptes() should take a pgprot_t and rebuild the pte with 
> mk_pte() or similar ?
> 
>> +        addr += PAGE_SIZE;
>> +    }
>>   }
>>   void unmap_kernel_page(unsigned long va)

I investigated a bit further and can confirm now that the above won't 
always work, see comment 
https://elixir.bootlin.com/linux/v6.3-rc2/source/arch/powerpc/include/asm/nohash/32/pgtable.h#L147

And then you see 
https://elixir.bootlin.com/linux/v6.3-rc2/source/arch/powerpc/include/asm/nohash/pte-e500.h#L63

Christophe