From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-bw0-f180.google.com (mail-bw0-f180.google.com [209.85.218.180]) by ozlabs.org (Postfix) with ESMTP id 15A7CDDE00 for ; Fri, 10 Apr 2009 00:06:58 +1000 (EST) Received: by bwz28 with SMTP id 28so592840bwz.9 for ; Thu, 09 Apr 2009 07:06:56 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20090409124634.GF18304@zod.rchland.ibm.com> References: <20090408211521.D0EF411B8054@mail214-sin.bigfish.com> <20090409124634.GF18304@zod.rchland.ibm.com> Date: Thu, 9 Apr 2009 16:06:56 +0200 Message-ID: Subject: Re: [PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR) From: Roderick Colenbrander To: Josh Boyer Content-Type: multipart/alternative; boundary=001636c5a81cc3beb004671fc2c2 Cc: linux-fbdev-devel@lists.sourceforge.net, adaplas@gmail.com, Suneel , linuxppc-dev@ozlabs.org, Suneel <"[mailto:suneel.garapati@xilinx.com]"@xilinx.com>, akonovalov@ru.mvista.com, John Linn List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , --001636c5a81cc3beb004671fc2c2 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit On Thu, Apr 9, 2009 at 2:46 PM, Josh Boyer wrote: > On Wed, Apr 08, 2009 at 03:11:25PM -0600, John Linn wrote: > >From: Suneel <[mailto:suneel.garapati@xilinx.com]> > > > >Added support for the new xps tft controller. > > > >The new core has PLB interface support in addition to existing > >DCR interface. > > > >The driver has been modified to support this new core which > >can be connected on PLB or DCR bus. > > > >Signed-off-by: Suneel > >Signed-off-by: John Linn > >--- > > drivers/video/xilinxfb.c | 227 > ++++++++++++++++++++++++++++++++-------------- > > 1 files changed, 160 insertions(+), 67 deletions(-) > > > >diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c > >index a82c530..a28a834 100644 > >--- a/drivers/video/xilinxfb.c > >+++ b/drivers/video/xilinxfb.c > >@@ -1,17 +1,24 @@ > > /* > >- * xilinxfb.c > > * > >- * Xilinx TFT LCD frame buffer driver > >+ * Xilinx TFT frame buffer driver > > * > > * Author: MontaVista Software, Inc. > > * source@mvista.com > > * > > * 2002-2007 (c) MontaVista Software, Inc. > > * 2007 (c) Secret Lab Technologies, Ltd. > >+ * 2009 (c) Xilinx Inc. > > * > >- * This file is licensed under the terms of the GNU General Public > License > >- * version 2. This program is licensed "as is" without any warranty of > any > >- * kind, whether express or implied. > >+ * This program is free software; you can redistribute it > >+ * and/or modify it under the terms of the GNU General Public > >+ * License as published by the Free Software Foundation; > >+ * either version 2 of the License, or (at your option) any > >+ * later version. > >+ * > >+ * You should have received a copy of the GNU General Public > >+ * License along with this program; if not, write to the Free > >+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA > >+ * 02139, USA. > > */ > > What Stephen said. > > > #define NUM_REGS 2 > > #define REG_FB_ADDR 0 > >@@ -112,6 +123,11 @@ struct xilinxfb_drvdata { > > > > struct fb_info info; /* FB driver info record */ > > > >+ u32 regs_phys; /* phys. address of the control > >+ registers */ > > Is this driver usable on the 440 based Xilinx devices? If so, is it > possible > to have the physical address of the registers above 4GiB, so is common with > almost all the I/O on the other 440 boards? > > The driver works fine on 440 based Xilinx boards (the ML510 I use has a 440 core). It might be nice to move physical addresses above 4GB for devices but in all Xilinx tools and reference designs addresses below 4GB are used for periperhals and I think even below 2GB (or even below 1GB). It depends on the design. Roderick Colenbrander --001636c5a81cc3beb004671fc2c2 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable

On Thu, Apr 9, 2009 at 2:46 PM, Josh Boy= er <jwbo= yer@linux.vnet.ibm.com> wrote:
On Wed, Apr 08, 2009 at 03:11:25PM -0600,= John Linn wrote:
>From: Suneel <[mailto:= suneel.garapati@xilinx.com]>
>
>Added support for the new xps tft controller.
>
>The new core has PLB interface support in addition to existing
>DCR interface.
>
>The driver has been modified to support this new core which
>can be connected on PLB or DCR bus.
>
>Signed-off-by: Suneel <suneelg= @xilinx.com>
>Signed-off-by: John Linn <jo= hn.linn@xilinx.com>
>---
> drivers/video/xilinxfb.c | =A0227 ++++++++++++++++++++++++++++++++----= ----------
> 1 files changed, 160 insertions(+), 67 deletions(-)
>
>diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
>index a82c530..a28a834 100644
>--- a/drivers/video/xilinxfb.c
>+++ b/drivers/video/xilinxfb.c
>@@ -1,17 +1,24 @@
> /*
>- * xilinxfb.c
> =A0*
>- * Xilinx TFT LCD frame buffer driver
>+ * Xilinx TFT frame buffer driver
> =A0*
> =A0* Author: MontaVista Software, Inc.
> =A0* =A0 =A0 =A0 =A0 source@mvist= a.com
> =A0*
> =A0* 2002-2007 (c) MontaVista Software, Inc.
> =A0* 2007 (c) Secret Lab Technologies, Ltd.
>+ * 2009 (c) Xilinx Inc.
> =A0*
>- * This file is licensed under the terms of the GNU General Public Lic= ense
>- * version 2. =A0This program is licensed "as is" without an= y warranty of any
>- * kind, whether express or implied.
>+ * This program is free software; you can redistribute it
>+ * and/or modify it under the terms of the GNU General Public
>+ * License as published by the Free Software Foundation;
>+ * either version 2 of the License, or (at your option) any
>+ * later version.
>+ *
>+ * You should have received a copy of the GNU General Public
>+ * License along with this program; if not, write to the Free
>+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
>+ * 02139, USA.
> =A0*/

What Stephen said.

> #define NUM_REGS =A0 =A0 =A02
> #define REG_FB_ADDR =A0 0
>@@ -112,6 +123,11 @@ struct xilinxfb_drvdata {
>
> =A0 =A0 =A0 struct fb_info =A0info; =A0 =A0 =A0 =A0 =A0 /* FB driver i= nfo record */
>
>+ =A0 =A0 =A0u32 =A0 =A0 =A0 =A0 =A0 =A0 regs_phys; =A0 =A0 =A0/* phys.= address of the control
>+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0registers */

Is this driver usable on the 440 based Xilinx devices? =A0If so, is i= t possible
to have the physical address of the registers above 4GiB, so is common with=
almost all the I/O on the other 440 boards?


The driver works fine on= 440 based Xilinx boards (the ML510 I use has a 440 core). It might be nice= to move physical addresses above 4GB for devices but in all Xilinx tools a= nd reference designs addresses below 4GB are used for periperhals and I thi= nk even below 2GB (or even below 1GB). It depends on the design.

Roderick Colenbrander
--001636c5a81cc3beb004671fc2c2--