[PATCH v4 0/3] Add support for ML510 board

[PATCH v4 0/3] Add support for ML510 board

[Grant Likely]

Heck, I don't know if this stuff even works, but I've refactored
Roderick's patches into something closer to the structure that I'd like
to see.  There are still a few things that bother me, but I think it
is mostly there.

It at least boots on an ML507 board.

Roderick, can you please take a look?

Thanks,
g.

--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.

[PATCH v4 1/3] powerpc/virtex: Add support for Xilinx PCI host bridge

[Grant Likely]

From: Roderick Colenbrander <thunderbird2k@gmail.com>

This patch adds support for the Xilinx plbv46-pci-1.03.a PCI host
bridge IPcore.

Signed-off-by: Roderick Colenbrander <thunderbird2k@gmail.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
---

 arch/powerpc/include/asm/xilinx_pci.h |   21 +++++
 arch/powerpc/platforms/40x/virtex.c   |    2 +
 arch/powerpc/platforms/44x/virtex.c   |    2 +
 arch/powerpc/platforms/Kconfig        |    4 +
 arch/powerpc/sysdev/Makefile          |    1 
 arch/powerpc/sysdev/xilinx_pci.c      |  132 +++++++++++++++++++++++++++++++++
 6 files changed, 162 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/include/asm/xilinx_pci.h
 create mode 100644 arch/powerpc/sysdev/xilinx_pci.c


diff --git a/arch/powerpc/include/asm/xilinx_pci.h b/arch/powerpc/include/asm/xilinx_pci.h
new file mode 100644
index 0000000..7a8275c
--- /dev/null
+++ b/arch/powerpc/include/asm/xilinx_pci.h
@@ -0,0 +1,21 @@
+/*
+ * Xilinx pci external definitions
+ *
+ * Copyright 2009 Roderick Colenbrander
+ * Copyright 2009 Secret Lab Technologies Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef INCLUDE_XILINX_PCI
+#define INCLUDE_XILINX_PCI
+
+#ifdef CONFIG_XILINX_PCI
+extern void __init xilinx_pci_init(void);
+#else
+static inline void __init xilinx_pci_init(void) { return; }
+#endif
+
+#endif /* INCLUDE_XILINX_PCI */
diff --git a/arch/powerpc/platforms/40x/virtex.c b/arch/powerpc/platforms/40x/virtex.c
index fc7fb00..d0fc686 100644
--- a/arch/powerpc/platforms/40x/virtex.c
+++ b/arch/powerpc/platforms/40x/virtex.c
@@ -14,6 +14,7 @@
 #include <asm/prom.h>
 #include <asm/time.h>
 #include <asm/xilinx_intc.h>
+#include <asm/xilinx_pci.h>
 #include <asm/ppc4xx.h>
 
 static struct of_device_id xilinx_of_bus_ids[] __initdata = {
@@ -47,6 +48,7 @@ static int __init virtex_probe(void)
 define_machine(virtex) {
 	.name			= "Xilinx Virtex",
 	.probe			= virtex_probe,
+	.setup_arch		= xilinx_pci_init,
 	.init_IRQ		= xilinx_intc_init_tree,
 	.get_irq		= xilinx_intc_get_irq,
 	.restart		= ppc4xx_reset_system,
diff --git a/arch/powerpc/platforms/44x/virtex.c b/arch/powerpc/platforms/44x/virtex.c
index 68637fa..cf96cca 100644
--- a/arch/powerpc/platforms/44x/virtex.c
+++ b/arch/powerpc/platforms/44x/virtex.c
@@ -16,6 +16,7 @@
 #include <asm/prom.h>
 #include <asm/time.h>
 #include <asm/xilinx_intc.h>
+#include <asm/xilinx_pci.h>
 #include <asm/reg.h>
 #include <asm/ppc4xx.h>
 #include "44x.h"
@@ -53,6 +54,7 @@ static int __init virtex_probe(void)
 define_machine(virtex) {
 	.name			= "Xilinx Virtex440",
 	.probe			= virtex_probe,
+	.setup_arch		= xilinx_pci_init,
 	.init_IRQ		= xilinx_intc_init_tree,
 	.get_irq		= xilinx_intc_get_irq,
 	.calibrate_decr		= generic_calibrate_decr,
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index e3e8707..04a8061 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -329,4 +329,8 @@ config MCU_MPC8349EMITX
 	  also register MCU GPIOs with the generic GPIO API, so you'll able
 	  to use MCU pins as GPIOs.
 
+config XILINX_PCI
+	bool "Xilinx PCI host bridge support"
+	depends on PCI && XILINX_VIRTEX
+
 endmenu
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index b33b28a..2d1c87d 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_IPIC)		+= ipic.o
 obj-$(CONFIG_4xx)		+= uic.o
 obj-$(CONFIG_4xx_SOC)		+= ppc4xx_soc.o
 obj-$(CONFIG_XILINX_VIRTEX)	+= xilinx_intc.o
+obj-$(CONFIG_XILINX_PCI)	+= xilinx_pci.o
 obj-$(CONFIG_OF_RTC)		+= of_rtc.o
 ifeq ($(CONFIG_PCI),y)
 obj-$(CONFIG_4xx)		+= ppc4xx_pci.o
diff --git a/arch/powerpc/sysdev/xilinx_pci.c b/arch/powerpc/sysdev/xilinx_pci.c
new file mode 100644
index 0000000..1453b0e
--- /dev/null
+++ b/arch/powerpc/sysdev/xilinx_pci.c
@@ -0,0 +1,132 @@
+/*
+ * PCI support for Xilinx plbv46_pci soft-core which can be used on
+ * Xilinx Virtex ML410 / ML510 boards.
+ *
+ * Copyright 2009 Roderick Colenbrander
+ * Copyright 2009 Secret Lab Technologies Ltd.
+ *
+ * The pci bridge fixup code was copied from ppc4xx_pci.c and was written
+ * by Benjamin Herrenschmidt.
+ * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/ioport.h>
+#include <linux/of.h>
+#include <linux/pci.h>
+#include <mm/mmu_decl.h>
+#include <asm/io.h>
+#include <asm/xilinx_pci.h>
+
+#define XPLB_PCI_ADDR 0x10c
+#define XPLB_PCI_DATA 0x110
+#define XPLB_PCI_BUS  0x114
+
+#define PCI_HOST_ENABLE_CMD PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
+
+static struct of_device_id xilinx_pci_match[] = {
+	{ .compatible = "xlnx,plbv46-pci-1.03.a", },
+	{}
+};
+
+/**
+ * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration.
+ */
+static void xilinx_pci_fixup_bridge(struct pci_dev *dev)
+{
+	struct pci_controller *hose;
+	int i;
+
+	if (dev->devfn || dev->bus->self)
+		return;
+
+	hose = pci_bus_to_host(dev->bus);
+	if (!hose)
+		return;
+
+	if (!of_match_node(xilinx_pci_match, hose->dn))
+		return;
+
+	/* Hide the PCI host BARs from the kernel as their content doesn't
+	 * fit well in the resource management
+	 */
+	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+		dev->resource[i].start = 0;
+		dev->resource[i].end = 0;
+		dev->resource[i].flags = 0;
+	}
+
+	dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n",
+		 pci_name(dev));
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge);
+
+/**
+ * xilinx_pci_exclude_device - Don't do config access for non-root bus
+ *
+ * This is a hack.  Config access to any bus other than bus 0 does not
+ * currently work on the ML510 so we prevent it here.
+ */
+static int
+xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn)
+{
+	return (bus != 0);
+}
+
+/**
+ * xilinx_pci_init - Find and register a Xilinx PCI host bridge
+ */
+void __init xilinx_pci_init(void)
+{
+	struct pci_controller *hose;
+	struct resource r;
+	void __iomem *pci_reg;
+	struct device_node *pci_node;
+
+	pci_node = of_find_matching_node(NULL, xilinx_pci_match);
+	if(!pci_node)
+		return;
+
+	if (of_address_to_resource(pci_node, 0, &r)) {
+		pr_err("xilinx-pci: cannot resolve base address\n");
+		return;
+	}
+
+	hose = pcibios_alloc_controller(pci_node);
+	if (!hose) {
+		pr_err("xilinx-pci: pcibios_alloc_controller() failed\n");
+		return;
+	}
+
+	/* Setup config space */
+	setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR,
+			   r.start + XPLB_PCI_DATA,
+			   PPC_INDIRECT_TYPE_SET_CFG_TYPE);
+
+	/* According to the xilinx plbv46_pci documentation the soft-core starts
+	 * a self-init when the bus master enable bit is set. Without this bit
+	 * set the pci bus can't be scanned.
+	 */
+	early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);
+
+	/* Set the max latency timer to 255 */
+	early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);
+
+	/* Set the max bus number to 255 */
+	pci_reg = of_iomap(pci_node, 0);
+	out_8(pci_reg + XPLB_PCI_BUS, 0xff);
+	iounmap(pci_reg);
+
+	/* Nothing past the root bridge is working right now.  By default
+	 * exclude config access to anything except bus 0 */
+	if (!ppc_md.pci_exclude_device)
+		ppc_md.pci_exclude_device = xilinx_pci_exclude_device;
+
+	/* Register the host bridge with the linux kernel! */
+	pci_process_bridge_OF_ranges(hose, pci_node, 1);
+
+	pr_info("xilinx-pci: Registered PCI host bridge\n");
+}

[PATCH v4 2/3] powerpc/virtex: refactor intc driver and add support for i8259 cascading

[Grant Likely]

From: Grant Likely <grant.likely@secretlab.ca>

This patch refactors some of the xilinx_intc interrupt controller driver
and adds support for cascading an i8259 off one of the irq lines.

This patch was based on the ML510 support work done by Roderick
Colenbrander.

Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
---

 arch/powerpc/sysdev/xilinx_intc.c |   76 ++++++++++++++++++++++++++++---------
 1 files changed, 58 insertions(+), 18 deletions(-)


diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c
index c658b41..90b5772 100644
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ b/arch/powerpc/sysdev/xilinx_intc.c
@@ -25,6 +25,7 @@
 #include <linux/of.h>
 #include <asm/io.h>
 #include <asm/processor.h>
+#include <asm/i8259.h>
 #include <asm/irq.h>
 
 /*
@@ -191,20 +192,14 @@ struct irq_host * __init
 xilinx_intc_init(struct device_node *np)
 {
 	struct irq_host * irq;
-	struct resource res;
 	void * regs;
-	int rc;
 
 	/* Find and map the intc registers */
-	rc = of_address_to_resource(np, 0, &res);
-	if (rc) {
-		printk(KERN_ERR __FILE__ ": of_address_to_resource() failed\n");
+	regs = of_iomap(np, 0);
+	if (!regs) {
+		pr_err("xilinx_intc: could not map registers\n");
 		return NULL;
 	}
-	regs = ioremap(res.start, 32);
-
-	printk(KERN_INFO "Xilinx intc at 0x%08llx mapped to 0x%p\n",
-		(unsigned long long) res.start, regs);
 
 	/* Setup interrupt controller */
 	out_be32(regs + XINTC_IER, 0); /* disable all irqs */
@@ -217,6 +212,7 @@ xilinx_intc_init(struct device_node *np)
 	if (!irq)
 		panic(__FILE__ ": Cannot allocate IRQ host\n");
 	irq->host_data = regs;
+
 	return irq;
 }
 
@@ -227,23 +223,65 @@ int xilinx_intc_get_irq(void)
 	return irq_linear_revmap(master_irqhost, in_be32(regs + XINTC_IVR));
 }
 
+#if defined(CONFIG_PPC_I8259)
+/*
+ * Support code for cascading to 8259 interrupt controllers
+ */
+static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc)
+{
+	unsigned int cascade_irq = i8259_irq();
+	if (cascade_irq)
+		generic_handle_irq(cascade_irq);
+
+	/* Let xilinx_intc end the interrupt */
+	desc->chip->ack(irq);
+	desc->chip->unmask(irq);
+}
+
+static void __init xilinx_i8259_setup_cascade(void)
+{
+	struct device_node *cascade_node;
+	int cascade_irq;
+
+	/* Initialize i8259 controller */
+	cascade_node = of_find_compatible_node(NULL, NULL, "chrp,iic");
+	if (!cascade_node)
+		return;
+
+	cascade_irq = irq_of_parse_and_map(cascade_node, 0);
+	if (!cascade_irq) {
+		pr_err("virtex_ml510: Failed to map cascade interrupt\n");
+		goto out;
+	}
+
+	i8259_init(cascade_node, 0);
+	set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade);
+
+ out:
+	of_node_put(cascade_node);
+}
+#else
+static inline void xilinx_i8259_setup_cascade(void) { return; }
+#endif /* defined(CONFIG_PPC_I8259) */
+
+static struct of_device_id xilinx_intc_match[] __initconst = {
+	{ .compatible = "xlnx,opb-intc-1.00.c", },
+	{ .compatible = "xlnx,xps-intc-1.00.a", },
+	{}
+};
+
+/*
+ * Initialize master Xilinx interrupt controller
+ */
 void __init xilinx_intc_init_tree(void)
 {
 	struct device_node *np;
 
 	/* find top level interrupt controller */
-	for_each_compatible_node(np, NULL, "xlnx,opb-intc-1.00.c") {
+	for_each_matching_node(np, xilinx_intc_match) {
 		if (!of_get_property(np, "interrupts", NULL))
 			break;
 	}
-	if (!np) {
-		for_each_compatible_node(np, NULL, "xlnx,xps-intc-1.00.a") {
-			if (!of_get_property(np, "interrupts", NULL))
-				break;
-		}
-	}
-
-	/* xilinx interrupt controller needs to be top level */
 	BUG_ON(!np);
 
 	master_irqhost = xilinx_intc_init(np);
@@ -251,4 +289,6 @@ void __init xilinx_intc_init_tree(void)
 
 	irq_set_default_host(master_irqhost);
 	of_node_put(np);
+
+	xilinx_i8259_setup_cascade();
 }

[PATCH v4 3/3] powerpc/virtex: Add Xilinx ML510 reference design support

[Grant Likely]

From: Roderick Colenbrander <thunderbird2k@gmail.com>

Signed-off-by: Roderick Colenbrander <thunderbird2k@gmail.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
---

 arch/powerpc/platforms/44x/Kconfig        |   10 +++++++++-
 arch/powerpc/platforms/44x/Makefile       |    1 +
 arch/powerpc/platforms/44x/virtex_ml510.c |   29 +++++++++++++++++++++++++++++
 arch/powerpc/sysdev/xilinx_intc.c         |    5 +++++
 4 files changed, 44 insertions(+), 1 deletions(-)
 create mode 100644 arch/powerpc/platforms/44x/virtex_ml510.c


diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index 0d83a6a..af1c51d 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -156,7 +156,7 @@ config YOSEMITE
 #	  This option enables support for the IBM PPC440GX evaluation board.
 
 config XILINX_VIRTEX440_GENERIC_BOARD
-	bool "Generic Xilinx Virtex 440 board"
+	bool "Xilinx Virtex 5 support"
 	depends on 44x
 	default n
 	select XILINX_VIRTEX_5_FXT
@@ -171,6 +171,14 @@ config XILINX_VIRTEX440_GENERIC_BOARD
 	  Most Virtex 5 designs should use this unless it needs to do some
 	  special configuration at board probe time.
 
+config XILINX_ML510
+	bool "Xilinx ML510 board support"
+	depends on XILINX_VIRTEX440_GENERIC_BOARD
+	select PPC_PCI_CHOICE
+	select XILINX_PCI if PCI
+	select PPC_INDIRECT_PCI if PCI
+	select PPC_I8259 if PCI
+
 config PPC44x_SIMPLE
 	bool "Simple PowerPC 44x board support"
 	depends on 44x
diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile
index 01f51da..ee6185a 100644
--- a/arch/powerpc/platforms/44x/Makefile
+++ b/arch/powerpc/platforms/44x/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_EBONY)	+= ebony.o
 obj-$(CONFIG_SAM440EP) 	+= sam440ep.o
 obj-$(CONFIG_WARP)	+= warp.o
 obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o
+obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o
diff --git a/arch/powerpc/platforms/44x/virtex_ml510.c b/arch/powerpc/platforms/44x/virtex_ml510.c
new file mode 100644
index 0000000..ba4a6e3
--- /dev/null
+++ b/arch/powerpc/platforms/44x/virtex_ml510.c
@@ -0,0 +1,29 @@
+#include <asm/i8259.h>
+#include <linux/pci.h>
+#include "44x.h"
+
+/**
+ * ml510_ail_quirk
+ */
+static void __devinit ml510_ali_quirk(struct pci_dev *dev)
+{
+	/* Enable the IDE controller */
+	pci_write_config_byte(dev, 0x58, 0x4c);
+	/* Assign irq 14 to the primary ide channel */
+	pci_write_config_byte(dev, 0x44, 0x0d);
+	/* Assign irq 15 to the secondary ide channel */
+	pci_write_config_byte(dev, 0x75, 0x0f);
+	/* Set the ide controller in native mode */
+	pci_write_config_byte(dev, 0x09, 0xff);
+
+	/* INTB = disabled, INTA = disabled */
+	pci_write_config_byte(dev, 0x48, 0x00);
+	/* INTD = disabled, INTC = disabled */
+	pci_write_config_byte(dev, 0x4a, 0x00);
+	/* Audio = INT7, Modem = disabled. */
+	pci_write_config_byte(dev, 0x4b, 0x60);
+	/* USB = INT7 */
+	pci_write_config_byte(dev, 0x74, 0x06);
+}
+DECLARE_PCI_FIXUP_EARLY(0x10b9, 0x1533, ml510_ali_quirk);
+
diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c
index 90b5772..3ee1fd3 100644
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ b/arch/powerpc/sysdev/xilinx_intc.c
@@ -257,6 +257,11 @@ static void __init xilinx_i8259_setup_cascade(void)
 	i8259_init(cascade_node, 0);
 	set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade);
 
+	/* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
+	/* This looks like a dirty hack to me --gcl */
+	outb(0xc0, 0x4d0);
+	outb(0xc0, 0x4d1);
+
  out:
 	of_node_put(cascade_node);
 }

RE: [PATCH v4 3/3] powerpc/virtex: Add Xilinx ML510 reference designsupport

[Stephen Neuendorffer]

> -----Original Message-----
> From: linuxppc-dev-bounces+stephen.neuendorffer=3Dxilinx.com@ozlabs.org
[mailto:linuxppc-dev-
> bounces+stephen.neuendorffer=3Dxilinx.com@ozlabs.org] On Behalf Of Grant
Likely
> Sent: Thursday, May 21, 2009 9:25 AM
> To: linuxppc-dev@ozlabs.org; Roderick Colenbrander
> Subject: [PATCH v4 3/3] powerpc/virtex: Add Xilinx ML510 reference
designsupport
> =

> From: Roderick Colenbrander <thunderbird2k@gmail.com>
> =

> Signed-off-by: Roderick Colenbrander <thunderbird2k@gmail.com>
> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> ---
> =

>  arch/powerpc/platforms/44x/Kconfig        |   10 +++++++++-
>  arch/powerpc/platforms/44x/Makefile       |    1 +
>  arch/powerpc/platforms/44x/virtex_ml510.c |   29
+++++++++++++++++++++++++++++
>  arch/powerpc/sysdev/xilinx_intc.c         |    5 +++++
>  4 files changed, 44 insertions(+), 1 deletions(-)
>  create mode 100644 arch/powerpc/platforms/44x/virtex_ml510.c
> =

> =

> diff --git a/arch/powerpc/platforms/44x/Kconfig
b/arch/powerpc/platforms/44x/Kconfig
> index 0d83a6a..af1c51d 100644
> --- a/arch/powerpc/platforms/44x/Kconfig
> +++ b/arch/powerpc/platforms/44x/Kconfig
> @@ -156,7 +156,7 @@ config YOSEMITE
>  #	  This option enables support for the IBM PPC440GX evaluation
board.
> =

>  config XILINX_VIRTEX440_GENERIC_BOARD
> -	bool "Generic Xilinx Virtex 440 board"
> +	bool "Xilinx Virtex 5 support"

'Virtex 5' is a little ambiguous..  I'd suggest keeping the old wording,
or saying 'Virtex 5 FXT support'.  Even then it's somewhat ambiguous,
since you could conceivably run linux on microblaze on V5FXT and use the
powerpc for something else..

>  	depends on 44x
>  	default n
>  	select XILINX_VIRTEX_5_FXT
> @@ -171,6 +171,14 @@ config XILINX_VIRTEX440_GENERIC_BOARD
>  	  Most Virtex 5 designs should use this unless it needs to do
some
>  	  special configuration at board probe time.
> =

> +config XILINX_ML510
> +	bool "Xilinx ML510 board support"
> +	depends on XILINX_VIRTEX440_GENERIC_BOARD
> +	select PPC_PCI_CHOICE
> +	select XILINX_PCI if PCI
> +	select PPC_INDIRECT_PCI if PCI
> +	select PPC_I8259 if PCI
> +
>  config PPC44x_SIMPLE
>  	bool "Simple PowerPC 44x board support"
>  	depends on 44x
> diff --git a/arch/powerpc/platforms/44x/Makefile
b/arch/powerpc/platforms/44x/Makefile
> index 01f51da..ee6185a 100644
> --- a/arch/powerpc/platforms/44x/Makefile
> +++ b/arch/powerpc/platforms/44x/Makefile
> @@ -4,3 +4,4 @@ obj-$(CONFIG_EBONY)	+=3D ebony.o
>  obj-$(CONFIG_SAM440EP) 	+=3D sam440ep.o
>  obj-$(CONFIG_WARP)	+=3D warp.o
>  obj-$(CONFIG_XILINX_VIRTEX_5_FXT) +=3D virtex.o
> +obj-$(CONFIG_XILINX_ML510) +=3D virtex_ml510.o
> diff --git a/arch/powerpc/platforms/44x/virtex_ml510.c
b/arch/powerpc/platforms/44x/virtex_ml510.c
> new file mode 100644
> index 0000000..ba4a6e3
> --- /dev/null
> +++ b/arch/powerpc/platforms/44x/virtex_ml510.c
> @@ -0,0 +1,29 @@
> +#include <asm/i8259.h>
> +#include <linux/pci.h>
> +#include "44x.h"
> +
> +/**
> + * ml510_ail_quirk

Tpyo, but is the comment even necessary if it doesn't say anything
useful?

> + */
> +static void __devinit ml510_ali_quirk(struct pci_dev *dev)
> +{
> +	/* Enable the IDE controller */
> +	pci_write_config_byte(dev, 0x58, 0x4c);
> +	/* Assign irq 14 to the primary ide channel */
> +	pci_write_config_byte(dev, 0x44, 0x0d);
> +	/* Assign irq 15 to the secondary ide channel */
> +	pci_write_config_byte(dev, 0x75, 0x0f);
> +	/* Set the ide controller in native mode */
> +	pci_write_config_byte(dev, 0x09, 0xff);
> +
> +	/* INTB =3D disabled, INTA =3D disabled */
> +	pci_write_config_byte(dev, 0x48, 0x00);
> +	/* INTD =3D disabled, INTC =3D disabled */
> +	pci_write_config_byte(dev, 0x4a, 0x00);
> +	/* Audio =3D INT7, Modem =3D disabled. */
> +	pci_write_config_byte(dev, 0x4b, 0x60);
> +	/* USB =3D INT7 */
> +	pci_write_config_byte(dev, 0x74, 0x06);
> +}
> +DECLARE_PCI_FIXUP_EARLY(0x10b9, 0x1533, ml510_ali_quirk);
> +
> diff --git a/arch/powerpc/sysdev/xilinx_intc.c
b/arch/powerpc/sysdev/xilinx_intc.c
> index 90b5772..3ee1fd3 100644
> --- a/arch/powerpc/sysdev/xilinx_intc.c
> +++ b/arch/powerpc/sysdev/xilinx_intc.c
> @@ -257,6 +257,11 @@ static void __init
xilinx_i8259_setup_cascade(void)
>  	i8259_init(cascade_node, 0);
>  	set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade);
> =

> +	/* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
> +	/* This looks like a dirty hack to me --gcl */
> +	outb(0xc0, 0x4d0);
> +	outb(0xc0, 0x4d1);
> +

Yeow... I agree about the dirty hack part...  shouldn't this be in the
device tree somewhere, or in the ali driver?

I'm curious if this works on ml410 as well..  (Yes, I know, does this
really matter much?  But there are still a bunch of them floating around
in universities.)  It may be nice to factor this out so ml410/ppc405 and
microblaze can get it as well.

Steve

>   out:
>  	of_node_put(cascade_node);
>  }
> =

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Re: [PATCH v4 0/3] Add support for ML510 board

[Roderick Colenbrander]

On Thu, May 21, 2009 at 6:24 PM, Grant Likely <grant.likely@secretlab.ca> w=
rote:
> Heck, I don't know if this stuff even works, but I've refactored
> Roderick's patches into something closer to the structure that I'd like
> to see. =A0There are still a few things that bother me, but I think it
> is mostly there.
>
> It at least boots on an ML507 board.
>
> Roderick, can you please take a look?
>
> Thanks,
> g.
>
> --
> Grant Likely, B.Sc. P.Eng.
> Secret Lab Technologies Ltd.
>

>From a quick glance it looks good. I will test it on monday.

Roderick

Re: [PATCH v4 3/3] powerpc/virtex: Add Xilinx ML510 reference designsupport

[Roderick Colenbrander]

> Yeow... I agree about the dirty hack part...  shouldn't this be in the
> device tree somewhere, or in the ali driver?
>
> I'm curious if this works on ml410 as well..  (Yes, I know, does this
> really matter much?  But there are still a bunch of them floating around
> in universities.)  It may be nice to factor this out so ml410/ppc405 and
> microblaze can get it as well.
>
> Steve

Yes the code can work one the ML410 as well. The thing is that you
would need a recent reference design from Xilinx. Before Xilinx used a
OPB pci bridge and these days they use a PLB (v46) pci bridge. The old
reference designs use the OPB core. I saw someone using a ML410
reference design which used the PBL pci soft-core and the same memory
addresses were even used as in the ml510 reference design I'm using.
I'm not sure where the guy got the design since the xilinx site only
shows old opb_pci stuff. (though the core is nearly the same) Further
most devices are also at the same locations on the pci bus.

Further the ml410 also offers good old lpt1 and some other things
which aren't on the ml510 but yes the pci code and big parts of the
dts file I wrote can be reused.

Roderick

Re: [PATCH v4 3/3] powerpc/virtex: Add Xilinx ML510 reference designsupport

[Grant Likely]

On Thu, May 21, 2009 at 10:50 AM, Stephen Neuendorffer
<stephen.neuendorffer@xilinx.com> wrote:
>> diff --git a/arch/powerpc/platforms/44x/Kconfig
> b/arch/powerpc/platforms/44x/Kconfig
>> index 0d83a6a..af1c51d 100644
>> --- a/arch/powerpc/platforms/44x/Kconfig
>> +++ b/arch/powerpc/platforms/44x/Kconfig
>> @@ -156,7 +156,7 @@ config YOSEMITE
>> =A0# =A0 =A0 =A0This option enables support for the IBM PPC440GX evaluat=
ion
> board.
>>
>> =A0config XILINX_VIRTEX440_GENERIC_BOARD
>> - =A0 =A0 bool "Generic Xilinx Virtex 440 board"
>> + =A0 =A0 bool "Xilinx Virtex 5 support"
>
> 'Virtex 5' is a little ambiguous.. =A0I'd suggest keeping the old wording=
,
> or saying 'Virtex 5 FXT support'. =A0Even then it's somewhat ambiguous,
> since you could conceivably run linux on microblaze on V5FXT and use the
> powerpc for something else..

Considering that this option only appears when AMCC 44x is selected, I
think the ambiguity is minimal.  :-)
I'll add the FXT though.

>> diff --git a/arch/powerpc/platforms/44x/virtex_ml510.c
> b/arch/powerpc/platforms/44x/virtex_ml510.c
>> new file mode 100644
>> index 0000000..ba4a6e3
>> --- /dev/null
>> +++ b/arch/powerpc/platforms/44x/virtex_ml510.c
>> @@ -0,0 +1,29 @@
>> +#include <asm/i8259.h>
>> +#include <linux/pci.h>
>> +#include "44x.h"
>> +
>> +/**
>> + * ml510_ail_quirk
>
> Tpyo, but is the comment even necessary if it doesn't say anything
> useful?

Oops; I started writing a comment and then never completed it.
Roderick; care to contribute some lines as to the purpose of this
block?

>> diff --git a/arch/powerpc/sysdev/xilinx_intc.c
> b/arch/powerpc/sysdev/xilinx_intc.c
>> index 90b5772..3ee1fd3 100644
>> --- a/arch/powerpc/sysdev/xilinx_intc.c
>> +++ b/arch/powerpc/sysdev/xilinx_intc.c
>> @@ -257,6 +257,11 @@ static void __init
> xilinx_i8259_setup_cascade(void)
>> =A0 =A0 =A0 i8259_init(cascade_node, 0);
>> =A0 =A0 =A0 set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade);
>>
>> + =A0 =A0 /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive *=
/
>> + =A0 =A0 /* This looks like a dirty hack to me --gcl */
>> + =A0 =A0 outb(0xc0, 0x4d0);
>> + =A0 =A0 outb(0xc0, 0x4d1);
>> +
>
> Yeow... I agree about the dirty hack part... =A0shouldn't this be in the
> device tree somewhere, or in the ali driver?

Chatting with Roderick on IRC today, it may be that these two lines
aren't even necessary.  They come from an old guide for porting Linux
to the ml410 in the pre-arch/powerpc days.  Now that IRQ sense is
encoded into the device tree, this probably isn't needed.

> I'm curious if this works on ml410 as well.. =A0(Yes, I know, does this
> really matter much? =A0But there are still a bunch of them floating aroun=
d
> in universities.)

It should do (at least I hope it does).  If I get my hands on an
ML410, then I'll try it out.

> =A0It may be nice to factor this out so ml410/ppc405 and
> microblaze can get it as well.

indeed.

--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH v4 3/3] powerpc/virtex: Add Xilinx ML510 reference designsupport

[Roderick Colenbrander]

Hi Stephen,

Grant forgot to attach the dts file (but a next patch will add it).
The dts file contains some lines for the pci bus mapping. The lines
are attached below. For pci support I'm using the reference bsb with
pci 'ML510 BSB1 Pcores Design' for PowerPC at:
http://www.xilinx.com/products/boards/ml510/ml510_10.1_3_1/bsb.htm.
The patch also contains a tutorial on how to add pci yourself.

As I mention in the comment of the plbv46_pci stuff C_IPIFBAR2PCIBAR_0
is not set correctly. Benjamin Herrenschmidt told me that inbound and
outbound pci transactions shouldn't overlap. With the value at ipif
plb 0xa0000000 maps to 0 on the pci side while the pci soft-core also
thinks that 0 maps to address 0 of the system memory. Setting
C_IPIFBAR2PCIBAR_0 to e.g. 0xa0000000 like I'm doing maps ipif plb
0xa0000000 to 0xa0000000 on the pci side and prevents this confusion.
The same is also wrong in the guides for the ml410.

Could you forward it to the right people so that this can get fixed?
No other changes are needed except for this one.

Roderick


+               plbv46_pci_0: plbv46-pci@85e00000 {
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       compatible = "xlnx,plbv46-pci-1.03.a";
+                       device_type = "pci";
+                       reg = < 0x85e00000 0x10000 >;
+                       /* The default ML510 BSB has
C_IPIFBAR2PCIBAR_0 set to 0 which means that a read/write to
+                        * the memory mapped i/o region (which starts
at 0xa0000000) for pci bar 0 on the plb side
+                        * translates to 0.
+                        * It is important to this value to
0xa0000000, so that inbound and outbound pci transactions
+                        * work properly including DMA.
+                        */
+                       ranges = <0x02000000 0x00000000 0xa0000000
0xa0000000 0x00000000 0x20000000
+                                 0x01000000 0x00000000 0x00000000
0xf0000000 0x00000000 0x00010000>;
+
+                       #interrupt-cells = <1>;
+                       interrupt-parent = <&xps_intc_0>;
+                       interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+                       interrupt-map = <
+                               /* IRQ mapping for pci slots and ALI
M1533 periperhals. In total there are
+                                * 5 interrupt lines connected to a
xps_intc controller. Four of them are PCI
+                                * IRQ A, B, C, D and which correspond
to respectively xpx_intc 5, 4, 3 and 2.
+                                * The fifth interrupt line is
connected to the south bridge and this one
+                                * uses irq 1 and is active high
instead of active low.
+                                *
+                                * The M1533 contains various
peripherals including AC97 audio, a modem, USB,
+                                * IDE and some power management
stuff. The modem isn't connected on the ML510
+                                * and the power management core also
isn't used.
+                                */
+
+                               /* IDSEL 0x16 / dev=6, bus=0 / PCI slot 3 */
+                               0x3000 0 0 1 &xps_intc_0 3 2
+                               0x3000 0 0 2 &xps_intc_0 2 2
+                               0x3000 0 0 3 &xps_intc_0 5 2
+                               0x3000 0 0 4 &xps_intc_0 4 2
+
+                               /* IDSEL 0x13 / dev=3, bus=1 / PCI slot 4 */
+                               /*
+                               0x11800 0 0 1 &xps_intc_0 5 0 2
+                               0x11800 0 0 2 &xps_intc_0 4 0 2
+                               0x11800 0 0 3 &xps_intc_0 3 0 2
+                               0x11800 0 0 4 &xps_intc_0 2 0 2
+                               */
+
+                               /* According to the datasheet +
schematic ABCD [FPGA] of slot 5 is mapped to DABC.
+                                * Testing showed that at least A maps
to B, the mapping of the other pins is a guess
+                                * and for that reason the lines have
been commented.
+                                */
+                               /* IDSEL 0x15 / dev=5, bus=0 / PCI slot 5 */
+                               0x2800 0 0 1 &xps_intc_0 4 2
+                               /*
+                               0x2800 0 0 2 &xps_intc_0 3 2
+                               0x2800 0 0 3 &xps_intc_0 2 2
+                               0x2800 0 0 4 &xps_intc_0 5 2
+                               */
+
+                               /* IDSEL 0x12 / dev=2, bus=1 / PCI slot 6 */
+                               /*
+                               0x11000 0 0 1 &xps_intc_0 4 0 2
+                               0x11000 0 0 2 &xps_intc_0 3 0 2
+                               0x11000 0 0 3 &xps_intc_0 2 0 2
+                               0x11000 0 0 4 &xps_intc_0 5 0 2
+                               */
+
+                               /* IDSEL 0x11 / dev=1, bus=0 / AC97 audio */
+                               0x0800 0 0 1 &i8259 7 2
+
+                               /* IDSEL 0x1b / dev=11, bus=0 / IDE */
+                               0x5800 0 0 1 &i8259 14 2
+
+                               /* IDSEL 0x1f / dev 15, bus=0 / 2x USB 1.1 */
+                               0x7800 0 0 1 &i8259 7 2
+                       >;
+                       ali_m1533 {
+                               #size-cells = <1>;
+                               #address-cells = <2>;
+                               i8259: interrupt-controller@20 {
+                                       reg = <1 0x20 2
+                                                       1 0xa0 2
+                                                       1 0x4d0 2>;
+                                       interrupt-controller;
+                                       device_type = "interrupt-controller";
+                                       #address-cells = <0>;
+                                       #interrupt-cells = <2>;
+                                       compatible = "chrp,iic";
+
+                                       /* The south bridge connection
is active high */
+                                       interrupts = <1 3>;
+                                       interrupt-parent = <&xps_intc_0>;
+                               };
+                       };
+               } ;