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From: Roderick Colenbrander <thunderbird2k@gmail.com>
To: Grant Likely <grant.likely@secretlab.ca>
Cc: linuxppc-dev@ozlabs.org
Subject: Re: [PATCH v5 0/4] Series short description
Date: Tue, 26 May 2009 14:50:35 +0200	[thread overview]
Message-ID: <c8485d470905260550w664e1f32o2176a8a28a13fb31@mail.gmail.com> (raw)
In-Reply-To: <c8485d470905260541t65e35d86l8c676a2b016c0ff8@mail.gmail.com>

On Tue, May 26, 2009 at 2:41 PM, Roderick Colenbrander
<thunderbird2k@gmail.com> wrote:
> On Mon, May 25, 2009 at 10:47 PM, Roderick Colenbrander
> <thunderbird2k@gmail.com> wrote:
>> On Mon, May 25, 2009 at 4:41 PM, Grant Likely <grant.likely@secretlab.ca=
> wrote:
>>> Repost of ml510 series. =A0This time against 2.6.30-rc7 and with the .d=
ts
>>> file included.
>>>
>>> g.
>>>
>>> --
>>> Grant Likely, B.Sc. P.Eng.
>>> Secret Lab Technologies Ltd.
>>>
>>
>> Thanks, I will check it out tomorrow.
>>
>> Roderick
>>
>
> Hi,
>
> I have tested the ml510 patches. The code works properly but I had to
> make a few slight changes to get it functioning. The most important
> change was in xilinx_intc driver. For level interrupts the ack command
> was removed during the xilinx_intc rewrite which caused a null pointer
> derefence in the i8259 cascade code. I have now changed it to:
> /* Let xilinx_intc end the interrupt */
> desc->chip->mask(irq);
> desc->chip->unmask(irq);
>
> This seems to work properly. Further the driver now also has proper
> level support, so i think my dts file has some errors. The pci
> interrupts (a/b/c/d) are all active low, so they need to be changed to
> '3' for the sense level. Further the i8259 is active high which needs
> to be set to 2 instead of 3.
>
> Further I have tested the need for the outb to 0x4d0/0x4d1. Removing
> those lines causes interrupt timeouts and ide won't function.
> Freescale does the same in arch/powerpc/platforms/fsl_uli1575.c (which
> is a much newer version of this chipset) in quirk_final_uli1575 but
> they are doing it for some more interrupts. I think this code should
> be done using a similar quirk in virtex_ml510.c
>
> Roderick
>

I have just tested the following and it seemed to work fine.
static void __devinit ml510_ali_quirk_final(struct pci_dev *dev)
{
	/* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
	/* This looks like a dirty hack to me --gcl */
	outb(0xc0, 0x4d0);
	outb(0xc0, 0x4d1);
}
DECLARE_PCI_FIXUP_FINAL(0x10b9, 0x1533, ml510_ali_quirk_final);

I'm not sure what is preferred level or edge interrupts as the ide
controller can be programmed to both (I would just have to write to
config register 0x44 and 0x75).

Roderick

      reply	other threads:[~2009-05-26 12:50 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-05-25 14:41 [PATCH v5 0/4] Series short description Grant Likely
2009-05-25 14:41 ` [PATCH v5 1/4] powerpc/virtex: Add support for Xilinx PCI host bridge Grant Likely
2009-05-25 14:41 ` [PATCH v5 2/4] powerpc/virtex: refactor intc driver and add support for i8259 cascading Grant Likely
2009-05-25 14:41 ` [PATCH v5 3/4] powerpc/virtex: Add Xilinx ML510 reference design support Grant Likely
2009-05-25 14:41 ` [PATCH v5 4/4] powerpc/virtex: Add ml510 reference design device tree Grant Likely
2009-05-25 20:47 ` [PATCH v5 0/4] Series short description Roderick Colenbrander
2009-05-26 12:41   ` Roderick Colenbrander
2009-05-26 12:50     ` Roderick Colenbrander [this message]

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