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From: Segher Boessenkool <segher@kernel.crashing.org>
Subject: Re: [RFC/PATCH] powerpc: MPC7450 L2 HW cache flush feature utilization
Date: Thu, 28 Jun 2007 10:24:06 +0200
To: Vladislav Buzov <vbuzov@ru.mvista.com>
Cc: linuxppc-dev list <linuxppc-dev@ozlabs.org>
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>>> Note that 745x processors have L3 cache installed and may have the 
>>> same
>>> problem requiring similar code modifications to use L3 hardware 
>>> flushing
>>> mechanism.
>>
>> What does the erratum say?
>
> The erratum says nothing about any HW bugs with L3 cache flush. I just 
> mentioned that the L3 cache flush operation described in MPC7450 
> Reference manual is similar to the L2 using the L3 cache hardware 
> flushing mechanism. For instance, it requires a complete L3 locking 
> before flushing.

Then I think we should use that mechanism in the Linux kernel.
Anything else is waiting for bugs to bite.

>> The L3 is a very different beast from the L2, IIRC it is
>> a pure victim cache so it cannot have this problem at all?
>
> I'm not sure if it is a pure victim cache. I read the MPC7450 
> reference manual and see that the L3 cache operates similarly to the 
> L2. The main difference between those caches is that L3 uses an 
> external SRAM memory while L2 is a pure on-chip cache.

Yeah but it isn't involved in any prefetching AFAIK.  Anyway,
moot point, since we really should do the recommended flush
algorithm (esp. since we clearly do not sufficiently understand
the details of the L3 operation!)


Segher