From: "Naresh Bhat" <nareshgbhat@gmail.com>
To: linuxppc-embedded@ozlabs.org
Subject: Board is not booting - Please Help me
Date: Wed, 30 Jul 2008 13:14:52 +0530 [thread overview]
Message-ID: <cf9b3c760807300044y4625ca2am60367defaa98d49b@mail.gmail.com> (raw)
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Hi Guys
I have ML507 board. By using "ml507_bsb_design_ppc440.zip"
I have created the "Base System Builder" project and also
I am able to create the following files sucessfully.
1. My own "DTS" file (attached with the mail)
2. My own "download.bit" file
3. My own ACE file. (Used the Montavista Pro 5.0 kernel., Kernel is compiled
with ARCH=powerpc, CROSS_COMPILE=ppc_440-, used the ml507_defconfig)
*My problem is:*
The ML507 board Booting and nothing will be displayed after device flat
tree(see the below Logs).
please help me on this what could be the problem?.
*LOGS:*
=======================================
* Welcome to the Xilinx Virtex-5 ML507 Evaluation Platform Bootloader Menu!
Please choose a demo by typing in the number of the demo you want to use
Or select a demo using the directional buttons (C,W,S,E,N)
(Then press the center (C) button to start the selected demo)
1. Virtex-5 Slide Show
2. Web Server Demo
3. Simon Game
4. Board Diagnostics (XROM)
5. USB Demo
6. My own ACE file
7. Ring Tone Player
Rebooting to System ACE Configuration Address 6...
booting virtex
memstart=0x10
memsize=0xf
zImage starting: loaded at 0x00400000 (sp: 0x00851eb8)
Allocating 0x33770c bytes for kernel ...
gunzipping (0x00000000 <- 0x0040d000:0x00580d73)...done 0x312590 bytes
Attached initrd image at 0x00581000-0x00850e21
initrd head: 0x1f8b0808
Linux/PowerPC load: console=ttyS0,9600 ip=off root=/dev/ram rw
Finalizing device tree... flat tree at 0x85e300*
======================================================================
--
Naresh Bhat
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/*
* (C) Copyright 2007-2008 Xilinx, Inc.
* (C) Copyright 2007-2008 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 10.1.02 EDK_K_SP2.5
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,virtex";
dcr-parent = <&ppc440_0>;
model = "testing";
DDR2_SDRAM: memory@0 {
device_type = "memory";
reg = < 0 10000000 >;
} ;
chosen {
bootargs = "console=ttyS0,9600 root=/dev/nfs rw";
} ;
cpus {
#address-cells = <1>;
#cpus = <1>;
#size-cells = <0>;
ppc440_0: cpu@0 {
#address-cells = <1>;
#size-cells = <1>;
clock-frequency = "";
compatible = "PowerPC,440", "ibm,ppc440";
d-cache-line-size = <20>;
d-cache-size = <8000>;
dcr-access-method = "native";
dcr-controller ;
device_type = "cpu";
i-cache-line-size = <20>;
i-cache-size = <8000>;
model = "PowerPC,440";
reg = <0>;
timebase-frequency = "";
xlnx,apu-control = <2000>;
xlnx,apu-udi-0 = <0>;
xlnx,apu-udi-1 = <0>;
xlnx,apu-udi-10 = <0>;
xlnx,apu-udi-11 = <0>;
xlnx,apu-udi-12 = <0>;
xlnx,apu-udi-13 = <0>;
xlnx,apu-udi-14 = <0>;
xlnx,apu-udi-15 = <0>;
xlnx,apu-udi-2 = <0>;
xlnx,apu-udi-3 = <0>;
xlnx,apu-udi-4 = <0>;
xlnx,apu-udi-5 = <0>;
xlnx,apu-udi-6 = <0>;
xlnx,apu-udi-7 = <0>;
xlnx,apu-udi-8 = <0>;
xlnx,apu-udi-9 = <0>;
xlnx,dcr-autolock-enable = <1>;
xlnx,dcu-rd-ld-cache-plb-prio = <0>;
xlnx,dcu-rd-noncache-plb-prio = <0>;
xlnx,dcu-rd-touch-plb-prio = <0>;
xlnx,dcu-rd-urgent-plb-prio = <0>;
xlnx,dcu-wr-flush-plb-prio = <0>;
xlnx,dcu-wr-store-plb-prio = <0>;
xlnx,dcu-wr-urgent-plb-prio = <0>;
xlnx,dma0-control = <0>;
xlnx,dma0-plb-prio = <0>;
xlnx,dma0-rxchannelctrl = <1010000>;
xlnx,dma0-rxirqtimer = <3ff>;
xlnx,dma0-txchannelctrl = <1010000>;
xlnx,dma0-txirqtimer = <3ff>;
xlnx,dma1-control = <0>;
xlnx,dma1-plb-prio = <0>;
xlnx,dma1-rxchannelctrl = <1010000>;
xlnx,dma1-rxirqtimer = <3ff>;
xlnx,dma1-txchannelctrl = <1010000>;
xlnx,dma1-txirqtimer = <3ff>;
xlnx,dma2-control = <0>;
xlnx,dma2-plb-prio = <0>;
xlnx,dma2-rxchannelctrl = <1010000>;
xlnx,dma2-rxirqtimer = <3ff>;
xlnx,dma2-txchannelctrl = <1010000>;
xlnx,dma2-txirqtimer = <3ff>;
xlnx,dma3-control = <0>;
xlnx,dma3-plb-prio = <0>;
xlnx,dma3-rxchannelctrl = <1010000>;
xlnx,dma3-rxirqtimer = <3ff>;
xlnx,dma3-txchannelctrl = <1010000>;
xlnx,dma3-txirqtimer = <3ff>;
xlnx,endian-reset = <0>;
xlnx,generate-plb-timespecs = <1>;
xlnx,icu-rd-fetch-plb-prio = <0>;
xlnx,icu-rd-spec-plb-prio = <0>;
xlnx,icu-rd-touch-plb-prio = <0>;
xlnx,interconnect-imask = <ffffffff>;
xlnx,mplb-allow-lock-xfer = <1>;
xlnx,mplb-arb-mode = <0>;
xlnx,mplb-awidth = <20>;
xlnx,mplb-counter = <500>;
xlnx,mplb-dwidth = <80>;
xlnx,mplb-max-burst = <8>;
xlnx,mplb-native-dwidth = <80>;
xlnx,mplb-p2p = <0>;
xlnx,mplb-prio-dcur = <2>;
xlnx,mplb-prio-dcuw = <3>;
xlnx,mplb-prio-icu = <4>;
xlnx,mplb-prio-splb0 = <1>;
xlnx,mplb-prio-splb1 = <0>;
xlnx,mplb-read-pipe-enable = <1>;
xlnx,mplb-sync-tattribute = <0>;
xlnx,mplb-wdog-enable = <1>;
xlnx,mplb-write-pipe-enable = <1>;
xlnx,mplb-write-post-enable = <1>;
xlnx,num-dma = <0>;
xlnx,pir = <f>;
xlnx,ppc440mc-addr-base = <0>;
xlnx,ppc440mc-addr-high = <fffffff>;
xlnx,ppc440mc-arb-mode = <0>;
xlnx,ppc440mc-bank-conflict-mask = <c00000>;
xlnx,ppc440mc-control = <f810008f>;
xlnx,ppc440mc-max-burst = <8>;
xlnx,ppc440mc-prio-dcur = <2>;
xlnx,ppc440mc-prio-dcuw = <3>;
xlnx,ppc440mc-prio-icu = <4>;
xlnx,ppc440mc-prio-splb0 = <1>;
xlnx,ppc440mc-prio-splb1 = <0>;
xlnx,ppc440mc-row-conflict-mask = <3ffe00>;
xlnx,ppcdm-asyncmode = <0>;
xlnx,ppcds-asyncmode = <0>;
xlnx,user-reset = <0>;
} ;
} ;
plb_v46_0: plb@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
ranges ;
DIP_Switches_8Bit: gpio@81460000 {
compatible = "xlnx,xps-gpio-1.00.a";
reg = < 81460000 10000 >;
xlnx,all-inputs = <1>;
xlnx,all-inputs-2 = <0>;
xlnx,dout-default = <0>;
xlnx,dout-default-2 = <0>;
xlnx,family = "virtex5";
xlnx,gpio-width = <8>;
xlnx,interrupt-present = <0>;
xlnx,is-bidir = <1>;
xlnx,is-bidir-2 = <1>;
xlnx,is-dual = <0>;
xlnx,tri-default = <ffffffff>;
xlnx,tri-default-2 = <ffffffff>;
} ;
IIC_EEPROM: i2c@81600000 {
compatible = "xlnx,xps-iic-2.00.a";
interrupt-parent = <&xps_intc_0>;
interrupts = < 1 2 >;
reg = < 81600000 10000 >;
xlnx,clk-freq = <5f5e100>;
xlnx,family = "virtex5";
xlnx,gpo-width = <1>;
xlnx,iic-freq = <186a0>;
xlnx,scl-inertial-delay = <0>;
xlnx,sda-inertial-delay = <0>;
xlnx,ten-bit-adr = <0>;
} ;
LEDs_8Bit: gpio@81400000 {
compatible = "xlnx,xps-gpio-1.00.a";
reg = < 81400000 10000 >;
xlnx,all-inputs = <0>;
xlnx,all-inputs-2 = <0>;
xlnx,dout-default = <0>;
xlnx,dout-default-2 = <0>;
xlnx,family = "virtex5";
xlnx,gpio-width = <8>;
xlnx,interrupt-present = <0>;
xlnx,is-bidir = <1>;
xlnx,is-bidir-2 = <1>;
xlnx,is-dual = <0>;
xlnx,tri-default = <ffffffff>;
xlnx,tri-default-2 = <ffffffff>;
} ;
LEDs_Positions: gpio@81420000 {
compatible = "xlnx,xps-gpio-1.00.a";
reg = < 81420000 10000 >;
xlnx,all-inputs = <0>;
xlnx,all-inputs-2 = <0>;
xlnx,dout-default = <0>;
xlnx,dout-default-2 = <0>;
xlnx,family = "virtex5";
xlnx,gpio-width = <5>;
xlnx,interrupt-present = <0>;
xlnx,is-bidir = <1>;
xlnx,is-bidir-2 = <1>;
xlnx,is-dual = <0>;
xlnx,tri-default = <ffffffff>;
xlnx,tri-default-2 = <ffffffff>;
} ;
Push_Buttons_5Bit: gpio@81440000 {
compatible = "xlnx,xps-gpio-1.00.a";
reg = < 81440000 10000 >;
xlnx,all-inputs = <1>;
xlnx,all-inputs-2 = <0>;
xlnx,dout-default = <0>;
xlnx,dout-default-2 = <0>;
xlnx,family = "virtex5";
xlnx,gpio-width = <5>;
xlnx,interrupt-present = <0>;
xlnx,is-bidir = <1>;
xlnx,is-bidir-2 = <1>;
xlnx,is-dual = <0>;
xlnx,tri-default = <ffffffff>;
xlnx,tri-default-2 = <ffffffff>;
} ;
RS232_Uart_1: serial@83e00000 {
clock-frequency = <5f5e100>;
compatible = "xlnx,xps-uart16550-2.00.a", "ns16550";
current-speed = <2580>;
device_type = "serial";
interrupt-parent = <&xps_intc_0>;
interrupts = < 3 2 >;
reg = < 83e00000 10000 >;
reg-offset = <3>;
reg-shift = <2>;
xlnx,family = "virtex5";
xlnx,has-external-rclk = <0>;
xlnx,has-external-xin = <0>;
xlnx,is-a-16550 = <1>;
} ;
RS232_Uart_2: serial@83e20000 {
clock-frequency = <5f5e100>;
compatible = "xlnx,xps-uart16550-2.00.a", "ns16550";
current-speed = <2580>;
device_type = "serial";
interrupt-parent = <&xps_intc_0>;
interrupts = < 2 2 >;
reg = < 83e20000 10000 >;
reg-offset = <3>;
reg-shift = <2>;
xlnx,family = "virtex5";
xlnx,has-external-rclk = <0>;
xlnx,has-external-xin = <0>;
xlnx,is-a-16550 = <1>;
} ;
SysACE_CompactFlash: sysace@83600000 {
compatible = "xlnx,xps-sysace-1.00.a";
interrupt-parent = <&xps_intc_0>;
interrupts = < 0 2 >;
reg = < 83600000 10000 >;
xlnx,family = "virtex5";
xlnx,mem-width = <10>;
} ;
xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
reg = < ffff0000 10000 >;
xlnx,family = "virtex5";
} ;
xps_intc_0: interrupt-controller@81800000 {
#interrupt-cells = <2>;
compatible = "xlnx,xps-intc-1.00.a";
interrupt-controller ;
reg = < 81800000 10000 >;
xlnx,num-intr-inputs = <4>;
} ;
} ;
} ;
next reply other threads:[~2008-07-30 7:44 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-07-30 7:44 Naresh Bhat [this message]
2008-08-01 2:34 ` Board is not booting - Please Help me Grant Likely
2008-08-01 15:00 ` John Linn
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