From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mailhub1.si.c-s.fr (pegase1.c-s.fr [93.17.236.30]) by lists.ozlabs.org (Postfix) with ESMTP id 042FB1A11BC for ; Sat, 18 Apr 2015 02:32:58 +1000 (AEST) Message-Id: Subject: [PATCH v5 0/5] powerpc8xx: Further optimisation of TLB handling To: Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , scottwood@freescale.com Date: Fri, 17 Apr 2015 18:32:50 +0200 (CEST) From: christophe.leroy@c-s.fr (root) Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , This patchset provides a further optimisation of TLB handling in the 8xx. Changes are: - Not saving registers like CR when not needed - Adding support to any TASK_SIZE Only the last patch of the set is changed compared to v4 Christophe Leroy (5): powerpc/8xx: macro for handling CPU15 errata powerpc/8xx: Handle CR out of exception PROLOG/EPILOG powerpc/8xx: dont save CR in SCRATCH registers powerpc/8xx: Use SPRG2 instead of DAR for saving r3 powerpc/8xx: Add support for TASK_SIZE greater than 0x80000000 arch/powerpc/kernel/head_8xx.S | 79 +++++++++++++++++++++++++++--------------- 1 file changed, 51 insertions(+), 28 deletions(-) -- 2.1.0