* [PATCH v2 01/10] powerpc: simplify BDI switch
2019-02-21 10:37 [PATCH v2 00/10] Optimise TLB miss handlers on 6xx (603/e300) Christophe Leroy
@ 2019-02-21 10:37 ` Christophe Leroy
2019-02-22 9:48 ` [v2,01/10] " Michael Ellerman
2019-02-21 10:37 ` [PATCH v2 02/10] powerpc/6xx: Don't use SPRN_SPRG2 for storing stack pointer while in RTAS Christophe Leroy
` (8 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Christophe Leroy @ 2019-02-21 10:37 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
There is no reason to re-read each time the pointer at
location 0xf0 as it is fixed and known.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/include/asm/mmu.h | 2 ++
arch/powerpc/kernel/head_32.S | 5 ++---
arch/powerpc/kernel/head_40x.S | 5 ++---
arch/powerpc/kernel/head_8xx.S | 1 +
arch/powerpc/mm/8xx_mmu.c | 7 ++-----
5 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 25607604a7a5..6d22a8e78fe2 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -356,6 +356,8 @@ extern void early_init_mmu_secondary(void);
extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
phys_addr_t first_memblock_size);
static inline void mmu_early_init_devtree(void) { }
+
+extern void *abatron_pteptrs[2];
#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 05b08db3901d..c2f564690778 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -1027,9 +1027,8 @@ _ENTRY(switch_mmu_context)
* The PGDIR is passed as second argument.
*/
lwz r4,MM_PGD(r4)
- lis r5, KERNELBASE@h
- lwz r5, 0xf0(r5)
- stw r4, 0x4(r5)
+ lis r5, abatron_pteptrs@ha
+ stw r4, abatron_pteptrs@l + 0x4(r5)
#endif
li r4,0
isync
diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S
index b19d78410511..11dd09d0ce1a 100644
--- a/arch/powerpc/kernel/head_40x.S
+++ b/arch/powerpc/kernel/head_40x.S
@@ -953,9 +953,8 @@ _GLOBAL(set_context)
/* Context switch the PTE pointer for the Abatron BDI2000.
* The PGDIR is the second parameter.
*/
- lis r5, KERNELBASE@h
- lwz r5, 0xf0(r5)
- stw r4, 0x4(r5)
+ lis r5, abatron_pteptrs@ha
+ stw r4, abatron_pteptrs@l + 0x4(r5)
#endif
sync
mtspr SPRN_PID,r3
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 20cc816b3508..ec12abc2a8ce 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -989,5 +989,6 @@ swapper_pg_dir:
/* Room for two PTE table poiners, usually the kernel and current user
* pointer to their respective root page table (pgdir).
*/
+ .globl abatron_pteptrs
abatron_pteptrs:
.space 8
diff --git a/arch/powerpc/mm/8xx_mmu.c b/arch/powerpc/mm/8xx_mmu.c
index bfa503cff351..f12ec85e965c 100644
--- a/arch/powerpc/mm/8xx_mmu.c
+++ b/arch/powerpc/mm/8xx_mmu.c
@@ -162,14 +162,11 @@ void set_context(unsigned long id, pgd_t *pgd)
{
s16 offset = (s16)(__pa(swapper_pg_dir));
-#ifdef CONFIG_BDI_SWITCH
- pgd_t **ptr = *(pgd_t ***)(KERNELBASE + 0xf0);
-
/* Context switch the PTE pointer for the Abatron BDI2000.
* The PGDIR is passed as second argument.
*/
- *(ptr + 1) = pgd;
-#endif
+ if (IS_ENABLED(CONFIG_BDI_SWITCH))
+ abatron_pteptrs[1] = pgd;
/* Register M_TWB will contain base address of level 1 table minus the
* lower part of the kernel PGDIR base address, so that all accesses to
--
2.13.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 02/10] powerpc/6xx: Don't use SPRN_SPRG2 for storing stack pointer while in RTAS
2019-02-21 10:37 [PATCH v2 00/10] Optimise TLB miss handlers on 6xx (603/e300) Christophe Leroy
2019-02-21 10:37 ` [PATCH v2 01/10] powerpc: simplify BDI switch Christophe Leroy
@ 2019-02-21 10:37 ` Christophe Leroy
2019-02-21 10:37 ` [PATCH v2 03/10] powerpc/6xx: Store PGDIR physical address in a SPRG Christophe Leroy
` (7 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Christophe Leroy @ 2019-02-21 10:37 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
When calling RTAS, the stack pointer is stored in SPRN_SPRG2
in order to be able to restore it in case of machine check in RTAS.
As machine check is not a perfomance critical path, this patch
frees SPRN_SPRG2 by using a field in thread struct instead.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/include/asm/processor.h | 3 +++
arch/powerpc/include/asm/reg.h | 1 -
arch/powerpc/kernel/asm-offsets.c | 3 +++
arch/powerpc/kernel/entry_32.S | 5 +++--
arch/powerpc/kernel/head_32.S | 22 ++++++++++++----------
5 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index ee58526cb6c2..e8682122ea3d 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -250,6 +250,9 @@ struct thread_struct {
#ifdef CONFIG_PPC32
void *pgdir; /* root of page-table tree */
unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
+#ifdef CONFIG_PPC_RTAS
+ unsigned long rtas_sp; /* stack pointer for when in RTAS */
+#endif
#endif
/* Debug Registers */
struct debug_reg debug;
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1c98ef1f2d5b..371ef6e8248e 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1167,7 +1167,6 @@
#ifdef CONFIG_PPC_BOOK3S_32
#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
-#define SPRN_SPRG_RTAS SPRN_SPRG2
#define SPRN_SPRG_603_LRU SPRN_SPRG4
#endif
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 9ffc72ded73a..d6f9bdb1eb2e 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -93,6 +93,9 @@ int main(void)
OFFSET(THREAD_INFO, task_struct, stack);
DEFINE(THREAD_INFO_GAP, _ALIGN_UP(sizeof(struct thread_info), 16));
OFFSET(KSP_LIMIT, thread_struct, ksp_limit);
+#ifdef CONFIG_PPC_RTAS
+ OFFSET(RTAS_SP, thread_struct, rtas_sp);
+#endif
#endif /* CONFIG_PPC64 */
#ifdef CONFIG_LIVEPATCH
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 0768dfd8a64e..394772b0a6e2 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -1335,7 +1335,7 @@ _GLOBAL(enter_rtas)
MTMSRD(r0) /* don't get trashed */
li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
mtlr r6
- mtspr SPRN_SPRG_RTAS,r7
+ stw r7, THREAD + RTAS_SP(r2)
mtspr SPRN_SRR0,r8
mtspr SPRN_SRR1,r9
RFI
@@ -1344,7 +1344,8 @@ _GLOBAL(enter_rtas)
lwz r9,8(r9) /* original msr value */
addi r1,r1,INT_FRAME_SIZE
li r0,0
- mtspr SPRN_SPRG_RTAS,r0
+ tophys(r7, r2)
+ stw r0, THREAD + RTAS_SP(r7)
mtspr SPRN_SRR0,r8
mtspr SPRN_SRR1,r9
RFI /* return to caller */
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index c2f564690778..04128899a0a5 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -352,9 +352,8 @@ i##n: \
* registers that might have bad values includes all the GPRs
* and all the BATs. We indicate that we are in RTAS by putting
* a non-zero value, the address of the exception frame to use,
- * in SPRG2. The machine check handler checks SPRG2 and uses its
- * value if it is non-zero. If we ever needed to free up SPRG2,
- * we could use a field in the thread_info or thread_struct instead.
+ * in thread.rtas_sp. The machine check handler checks thread.rtas_sp
+ * and uses its value if it is non-zero.
* (Other exception handlers assume that r1 is a valid kernel stack
* pointer when we take an exception from supervisor mode.)
* -- paulus.
@@ -365,16 +364,15 @@ i##n: \
mtspr SPRN_SPRG_SCRATCH1,r11
mfcr r10
#ifdef CONFIG_PPC_CHRP
- mfspr r11,SPRN_SPRG_RTAS
- cmpwi 0,r11,0
- bne 7f
+ mfspr r11, SPRN_SPRG_THREAD
+ lwz r11, RTAS_SP(r11)
+ cmpwi cr1, r11, 0
+ bne cr1, 7f
#endif /* CONFIG_PPC_CHRP */
EXCEPTION_PROLOG_1
7: EXCEPTION_PROLOG_2
addi r3,r1,STACK_FRAME_OVERHEAD
#ifdef CONFIG_PPC_CHRP
- mfspr r4,SPRN_SPRG_RTAS
- cmpwi cr1,r4,0
bne cr1,1f
#endif
EXC_XFER_STD(0x200, machine_check_exception)
@@ -865,8 +863,10 @@ __secondary_start:
tophys(r4,r2)
addi r4,r4,THREAD /* phys address of our thread_struct */
mtspr SPRN_SPRG_THREAD,r4
+#ifdef CONFIG_PPC_RTAS
li r3,0
- mtspr SPRN_SPRG_RTAS,r3 /* 0 => not in RTAS */
+ stw r3, RTAS_SP(r4) /* 0 => not in RTAS */
+#endif
/* enable MMU and jump to start_secondary */
li r4,MSR_KERNEL
@@ -950,8 +950,10 @@ start_here:
tophys(r4,r2)
addi r4,r4,THREAD /* init task's THREAD */
mtspr SPRN_SPRG_THREAD,r4
+#ifdef CONFIG_PPC_RTAS
li r3,0
- mtspr SPRN_SPRG_RTAS,r3 /* 0 => not in RTAS */
+ stw r3, RTAS_SP(r4) /* 0 => not in RTAS */
+#endif
/* stack */
lis r1,init_thread_union@ha
--
2.13.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 03/10] powerpc/6xx: Store PGDIR physical address in a SPRG
2019-02-21 10:37 [PATCH v2 00/10] Optimise TLB miss handlers on 6xx (603/e300) Christophe Leroy
2019-02-21 10:37 ` [PATCH v2 01/10] powerpc: simplify BDI switch Christophe Leroy
2019-02-21 10:37 ` [PATCH v2 02/10] powerpc/6xx: Don't use SPRN_SPRG2 for storing stack pointer while in RTAS Christophe Leroy
@ 2019-02-21 10:37 ` Christophe Leroy
2019-03-07 14:11 ` Guenter Roeck
2019-02-21 10:37 ` [PATCH v2 04/10] powerpc/603: use physical address directly in TLB miss handlers Christophe Leroy
` (6 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Christophe Leroy @ 2019-02-21 10:37 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
Use SPRN_SPRG2 to store the current thread PGDIR and
avoid reading thread_struct.pgdir at every TLB miss.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/include/asm/reg.h | 1 +
arch/powerpc/kernel/cpu_setup_6xx.S | 4 ++++
arch/powerpc/kernel/head_32.S | 25 ++++++++++++-------------
arch/powerpc/mm/hash_low_32.S | 3 +--
4 files changed, 18 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 371ef6e8248e..1f79e1d8fb0b 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1167,6 +1167,7 @@
#ifdef CONFIG_PPC_BOOK3S_32
#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
+#define SPRN_SPRG_PGDIR SPRN_SPRG2
#define SPRN_SPRG_603_LRU SPRN_SPRG4
#endif
diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S
index 8c069e96c478..6f1c11e0691f 100644
--- a/arch/powerpc/kernel/cpu_setup_6xx.S
+++ b/arch/powerpc/kernel/cpu_setup_6xx.S
@@ -24,6 +24,10 @@ BEGIN_MMU_FTR_SECTION
li r10,0
mtspr SPRN_SPRG_603_LRU,r10 /* init SW LRU tracking */
END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
+ lis r10, (swapper_pg_dir - PAGE_OFFSET)@h
+ ori r10, r10, (swapper_pg_dir - PAGE_OFFSET)@l
+ mtspr SPRN_SPRG_PGDIR, r10
+
BEGIN_FTR_SECTION
bl __init_fpu_registers
END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE)
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 04128899a0a5..2b0a26f66115 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -500,16 +500,15 @@ InstructionTLBMiss:
mfspr r3,SPRN_IMISS
lis r1,PAGE_OFFSET@h /* check if kernel address */
cmplw 0,r1,r3
- mfspr r2,SPRN_SPRG_THREAD
+ mfspr r2, SPRN_SPRG_PGDIR
li r1,_PAGE_USER|_PAGE_PRESENT|_PAGE_EXEC /* low addresses tested as user */
- lwz r2,PGDIR(r2)
bge- 112f
mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
lis r2,swapper_pg_dir@ha /* if kernel address, use */
addi r2,r2,swapper_pg_dir@l /* kernel page table */
-112: tophys(r2,r2)
- rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
+ tophys(r2,r2)
+112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
lwz r2,0(r2) /* get pmd entry */
rlwinm. r2,r2,0,0,19 /* extract address of pte page */
beq- InstructionAddressInvalid /* return if no mapping */
@@ -574,16 +573,15 @@ DataLoadTLBMiss:
mfspr r3,SPRN_DMISS
lis r1,PAGE_OFFSET@h /* check if kernel address */
cmplw 0,r1,r3
- mfspr r2,SPRN_SPRG_THREAD
+ mfspr r2, SPRN_SPRG_PGDIR
li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
- lwz r2,PGDIR(r2)
bge- 112f
mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
lis r2,swapper_pg_dir@ha /* if kernel address, use */
addi r2,r2,swapper_pg_dir@l /* kernel page table */
-112: tophys(r2,r2)
- rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
+ tophys(r2,r2)
+112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
lwz r2,0(r2) /* get pmd entry */
rlwinm. r2,r2,0,0,19 /* extract address of pte page */
beq- DataAddressInvalid /* return if no mapping */
@@ -658,16 +656,15 @@ DataStoreTLBMiss:
mfspr r3,SPRN_DMISS
lis r1,PAGE_OFFSET@h /* check if kernel address */
cmplw 0,r1,r3
- mfspr r2,SPRN_SPRG_THREAD
+ mfspr r2, SPRN_SPRG_PGDIR
li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
- lwz r2,PGDIR(r2)
bge- 112f
mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
lis r2,swapper_pg_dir@ha /* if kernel address, use */
addi r2,r2,swapper_pg_dir@l /* kernel page table */
-112: tophys(r2,r2)
- rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
+ tophys(r2,r2)
+112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
lwz r2,0(r2) /* get pmd entry */
rlwinm. r2,r2,0,0,19 /* extract address of pte page */
beq- DataAddressInvalid /* return if no mapping */
@@ -1024,14 +1021,16 @@ _ENTRY(switch_mmu_context)
li r0,NUM_USER_SEGMENTS
mtctr r0
+ lwz r4, MM_PGD(r4)
#ifdef CONFIG_BDI_SWITCH
/* Context switch the PTE pointer for the Abatron BDI2000.
* The PGDIR is passed as second argument.
*/
- lwz r4,MM_PGD(r4)
lis r5, abatron_pteptrs@ha
stw r4, abatron_pteptrs@l + 0x4(r5)
#endif
+ tophys(r4, r4)
+ mtspr SPRN_SPRG_PGDIR, r4
li r4,0
isync
3:
diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S
index 1e2df3e9f9ea..82e7dd0c0220 100644
--- a/arch/powerpc/mm/hash_low_32.S
+++ b/arch/powerpc/mm/hash_low_32.S
@@ -70,9 +70,8 @@ _GLOBAL(hash_page)
/* Get PTE (linux-style) and check access */
lis r0,KERNELBASE@h /* check if kernel address */
cmplw 0,r4,r0
- mfspr r8,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
- lwz r5,PGDIR(r8) /* virt page-table root */
+ mfspr r5, SPRN_SPRG_PGDIR /* virt page-table root */
blt+ 112f /* assume user more likely */
lis r5,swapper_pg_dir@ha /* if kernel address, use */
addi r5,r5,swapper_pg_dir@l /* kernel page table */
--
2.13.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v2 03/10] powerpc/6xx: Store PGDIR physical address in a SPRG
2019-02-21 10:37 ` [PATCH v2 03/10] powerpc/6xx: Store PGDIR physical address in a SPRG Christophe Leroy
@ 2019-03-07 14:11 ` Guenter Roeck
2019-03-07 18:14 ` Christophe Leroy
0 siblings, 1 reply; 16+ messages in thread
From: Guenter Roeck @ 2019-03-07 14:11 UTC (permalink / raw)
To: Christophe Leroy; +Cc: linuxppc-dev, Paul Mackerras, linux-kernel
Hi,
On Thu, Feb 21, 2019 at 10:37:55AM +0000, Christophe Leroy wrote:
> Use SPRN_SPRG2 to store the current thread PGDIR and
> avoid reading thread_struct.pgdir at every TLB miss.
>
This patch causes a number of silent (no crash) qemu boot stalls
in -next. See
https://kerneltests.org/builders/qemu-ppc-next/builds/1080/steps/qemubuildcommand/logs/stdio
for an example.
Unfortunately, it is not possible to revert the patch due to subsequent
patches, so I was unable to test a revert.
Bisect log is attached.
Guenter
---
# bad: [cf08baa29613dd899954089e7cc7dba1d478b365] Add linux-next specific files for 20190306
# good: [1c163f4c7b3f621efff9b28a47abb36f7378d783] Linux 5.0
git bisect start 'HEAD' 'v5.0'
# bad: [6cc8f3499ec8d31904ab9083980a91736512cb37] Merge remote-tracking branch 'vfs/for-next'
git bisect bad 6cc8f3499ec8d31904ab9083980a91736512cb37
# good: [63bdf4284c38a48af21745ceb148a087b190cd21] Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
git bisect good 63bdf4284c38a48af21745ceb148a087b190cd21
# good: [520b5fc601ab760fee7ea0c403b42d04e8ebfd93] Merge remote-tracking branch 'arm-soc/for-next'
git bisect good 520b5fc601ab760fee7ea0c403b42d04e8ebfd93
# bad: [d7f54e4e0d4e90f5df78da8d6a830bafad3b535a] Merge remote-tracking branch 'xtensa/xtensa-for-next'
git bisect bad d7f54e4e0d4e90f5df78da8d6a830bafad3b535a
# good: [0c1a78523542fb3d2e6c5ac7955c8ca8f6482e6f] Merge remote-tracking branch 'clk/clk-next'
git bisect good 0c1a78523542fb3d2e6c5ac7955c8ca8f6482e6f
# bad: [fb0b0a73b223fc113e961b1d921322844e9c30d9] powerpc: Enable kcov
git bisect bad fb0b0a73b223fc113e961b1d921322844e9c30d9
# good: [d0055df0c9c1471c389197a69f43e300185a75aa] Merge branch 'topic/dma' into next
git bisect good d0055df0c9c1471c389197a69f43e300185a75aa
# good: [0df977eafc792a5365a7f81d8d5920132e03afad] powerpc/6xx: Don't use SPRN_SPRG2 for storing stack pointer while in RTAS
git bisect good 0df977eafc792a5365a7f81d8d5920132e03afad
# bad: [665bed2386e5dc29844ad78c7ef1464664b103ec] powerpc/8xx: replace most #ifdef by IS_ENABLED() in 8xx_mmu.c
git bisect bad 665bed2386e5dc29844ad78c7ef1464664b103ec
# bad: [78ca1108b10927b3d068c8da91352b0f4cd01fc5] powerpc/book3s32: Reorder _PAGE_XXX flags to simplify TLB handling
git bisect bad 78ca1108b10927b3d068c8da91352b0f4cd01fc5
# bad: [a8a121995b2e4f227fddc534c6bd5f1c02cbe2ee] powerpc/603: Don't handle kernel page TLB misses when not need
git bisect bad a8a121995b2e4f227fddc534c6bd5f1c02cbe2ee
# bad: [2c12393f577396a51b7e0537bd3eb29dcc26dc1b] powerpc/603: use physical address directly in TLB miss handlers.
git bisect bad 2c12393f577396a51b7e0537bd3eb29dcc26dc1b
# bad: [93c4a162b014d238a287f8264adb25c009c79e61] powerpc/6xx: Store PGDIR physical address in a SPRG
git bisect bad 93c4a162b014d238a287f8264adb25c009c79e61
# first bad commit: [93c4a162b014d238a287f8264adb25c009c79e61] powerpc/6xx: Store PGDIR physical address in a SPRG
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 03/10] powerpc/6xx: Store PGDIR physical address in a SPRG
2019-03-07 14:11 ` Guenter Roeck
@ 2019-03-07 18:14 ` Christophe Leroy
2019-03-07 19:07 ` Guenter Roeck
0 siblings, 1 reply; 16+ messages in thread
From: Christophe Leroy @ 2019-03-07 18:14 UTC (permalink / raw)
To: Guenter Roeck; +Cc: linuxppc-dev, Paul Mackerras, linux-kernel
Hi,
On 03/07/2019 02:11 PM, Guenter Roeck wrote:
> Hi,
>
> On Thu, Feb 21, 2019 at 10:37:55AM +0000, Christophe Leroy wrote:
>> Use SPRN_SPRG2 to store the current thread PGDIR and
>> avoid reading thread_struct.pgdir at every TLB miss.
>>
> This patch causes a number of silent (no crash) qemu boot stalls
> in -next. See
> https://kerneltests.org/builders/qemu-ppc-next/builds/1080/steps/qemubuildcommand/logs/stdio
> for an example.
Oops.
Could you try the fix below ?
diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S
b/arch/powerpc/kernel/cpu_setup_6xx.S
index 6f1c11e0691f..7534ecff5e92 100644
--- a/arch/powerpc/kernel/cpu_setup_6xx.S
+++ b/arch/powerpc/kernel/cpu_setup_6xx.S
@@ -24,9 +24,6 @@ BEGIN_MMU_FTR_SECTION
li r10,0
mtspr SPRN_SPRG_603_LRU,r10 /* init SW LRU tracking */
END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
- lis r10, (swapper_pg_dir - PAGE_OFFSET)@h
- ori r10, r10, (swapper_pg_dir - PAGE_OFFSET)@l
- mtspr SPRN_SPRG_PGDIR, r10
BEGIN_FTR_SECTION
bl __init_fpu_registers
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index ce6a972f2584..48051c8977c5 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -855,6 +855,9 @@ __secondary_start:
li r3,0
stw r3, RTAS_SP(r4) /* 0 => not in RTAS */
#endif
+ lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
+ ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
+ mtspr SPRN_SPRG_PGDIR, r4
/* enable MMU and jump to start_secondary */
li r4,MSR_KERNEL
@@ -942,6 +945,9 @@ start_here:
li r3,0
stw r3, RTAS_SP(r4) /* 0 => not in RTAS */
#endif
+ lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
+ ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
+ mtspr SPRN_SPRG_PGDIR, r4
/* stack */
lis r1,init_thread_union@ha
diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S
index 1f13494efb2b..587e4550d83e 100644
--- a/arch/powerpc/mm/hash_low_32.S
+++ b/arch/powerpc/mm/hash_low_32.S
@@ -70,12 +70,12 @@ _GLOBAL(hash_page)
lis r0,KERNELBASE@h /* check if kernel address */
cmplw 0,r4,r0
ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
- mfspr r5, SPRN_SPRG_PGDIR /* virt page-table root */
+ mfspr r5, SPRN_SPRG_PGDIR /* phys page-table root */
blt+ 112f /* assume user more likely */
- lis r5,swapper_pg_dir@ha /* if kernel address, use */
- addi r5,r5,swapper_pg_dir@l /* kernel page table */
+ lis r5, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
+ addi r5 ,r5 , (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
-112: tophys(r5, r5)
+112:
#ifndef CONFIG_PTE_64BIT
rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
lwz r8,0(r5) /* get pmd entry */
Thanks
Christophe
>
> Unfortunately, it is not possible to revert the patch due to subsequent
> patches, so I was unable to test a revert.
>
> Bisect log is attached.
>
> Guenter
>
> ---
> # bad: [cf08baa29613dd899954089e7cc7dba1d478b365] Add linux-next specific files for 20190306
> # good: [1c163f4c7b3f621efff9b28a47abb36f7378d783] Linux 5.0
> git bisect start 'HEAD' 'v5.0'
> # bad: [6cc8f3499ec8d31904ab9083980a91736512cb37] Merge remote-tracking branch 'vfs/for-next'
> git bisect bad 6cc8f3499ec8d31904ab9083980a91736512cb37
> # good: [63bdf4284c38a48af21745ceb148a087b190cd21] Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
> git bisect good 63bdf4284c38a48af21745ceb148a087b190cd21
> # good: [520b5fc601ab760fee7ea0c403b42d04e8ebfd93] Merge remote-tracking branch 'arm-soc/for-next'
> git bisect good 520b5fc601ab760fee7ea0c403b42d04e8ebfd93
> # bad: [d7f54e4e0d4e90f5df78da8d6a830bafad3b535a] Merge remote-tracking branch 'xtensa/xtensa-for-next'
> git bisect bad d7f54e4e0d4e90f5df78da8d6a830bafad3b535a
> # good: [0c1a78523542fb3d2e6c5ac7955c8ca8f6482e6f] Merge remote-tracking branch 'clk/clk-next'
> git bisect good 0c1a78523542fb3d2e6c5ac7955c8ca8f6482e6f
> # bad: [fb0b0a73b223fc113e961b1d921322844e9c30d9] powerpc: Enable kcov
> git bisect bad fb0b0a73b223fc113e961b1d921322844e9c30d9
> # good: [d0055df0c9c1471c389197a69f43e300185a75aa] Merge branch 'topic/dma' into next
> git bisect good d0055df0c9c1471c389197a69f43e300185a75aa
> # good: [0df977eafc792a5365a7f81d8d5920132e03afad] powerpc/6xx: Don't use SPRN_SPRG2 for storing stack pointer while in RTAS
> git bisect good 0df977eafc792a5365a7f81d8d5920132e03afad
> # bad: [665bed2386e5dc29844ad78c7ef1464664b103ec] powerpc/8xx: replace most #ifdef by IS_ENABLED() in 8xx_mmu.c
> git bisect bad 665bed2386e5dc29844ad78c7ef1464664b103ec
> # bad: [78ca1108b10927b3d068c8da91352b0f4cd01fc5] powerpc/book3s32: Reorder _PAGE_XXX flags to simplify TLB handling
> git bisect bad 78ca1108b10927b3d068c8da91352b0f4cd01fc5
> # bad: [a8a121995b2e4f227fddc534c6bd5f1c02cbe2ee] powerpc/603: Don't handle kernel page TLB misses when not need
> git bisect bad a8a121995b2e4f227fddc534c6bd5f1c02cbe2ee
> # bad: [2c12393f577396a51b7e0537bd3eb29dcc26dc1b] powerpc/603: use physical address directly in TLB miss handlers.
> git bisect bad 2c12393f577396a51b7e0537bd3eb29dcc26dc1b
> # bad: [93c4a162b014d238a287f8264adb25c009c79e61] powerpc/6xx: Store PGDIR physical address in a SPRG
> git bisect bad 93c4a162b014d238a287f8264adb25c009c79e61
> # first bad commit: [93c4a162b014d238a287f8264adb25c009c79e61] powerpc/6xx: Store PGDIR physical address in a SPRG
>
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v2 03/10] powerpc/6xx: Store PGDIR physical address in a SPRG
2019-03-07 18:14 ` Christophe Leroy
@ 2019-03-07 19:07 ` Guenter Roeck
2019-03-07 19:10 ` Christophe Leroy
0 siblings, 1 reply; 16+ messages in thread
From: Guenter Roeck @ 2019-03-07 19:07 UTC (permalink / raw)
To: Christophe Leroy; +Cc: linuxppc-dev, Paul Mackerras, linux-kernel
On Thu, Mar 07, 2019 at 06:14:09PM +0000, Christophe Leroy wrote:
> Hi,
>
> On 03/07/2019 02:11 PM, Guenter Roeck wrote:
> >Hi,
> >
> >On Thu, Feb 21, 2019 at 10:37:55AM +0000, Christophe Leroy wrote:
> >>Use SPRN_SPRG2 to store the current thread PGDIR and
> >>avoid reading thread_struct.pgdir at every TLB miss.
> >>
> >This patch causes a number of silent (no crash) qemu boot stalls
> >in -next. See
> >https://kerneltests.org/builders/qemu-ppc-next/builds/1080/steps/qemubuildcommand/logs/stdio
> >for an example.
>
> Oops.
> Could you try the fix below ?
>
Yes, that does the trick. With this patch applied on top of next-20190306,
all my ppc qemu boot tests pass.
Tested-by: Guenter Roeck <linux@roeck-us.net>
Guenter
> diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S
> b/arch/powerpc/kernel/cpu_setup_6xx.S
> index 6f1c11e0691f..7534ecff5e92 100644
> --- a/arch/powerpc/kernel/cpu_setup_6xx.S
> +++ b/arch/powerpc/kernel/cpu_setup_6xx.S
> @@ -24,9 +24,6 @@ BEGIN_MMU_FTR_SECTION
> li r10,0
> mtspr SPRN_SPRG_603_LRU,r10 /* init SW LRU tracking */
> END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
> - lis r10, (swapper_pg_dir - PAGE_OFFSET)@h
> - ori r10, r10, (swapper_pg_dir - PAGE_OFFSET)@l
> - mtspr SPRN_SPRG_PGDIR, r10
>
> BEGIN_FTR_SECTION
> bl __init_fpu_registers
> diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
> index ce6a972f2584..48051c8977c5 100644
> --- a/arch/powerpc/kernel/head_32.S
> +++ b/arch/powerpc/kernel/head_32.S
> @@ -855,6 +855,9 @@ __secondary_start:
> li r3,0
> stw r3, RTAS_SP(r4) /* 0 => not in RTAS */
> #endif
> + lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
> + ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
> + mtspr SPRN_SPRG_PGDIR, r4
>
> /* enable MMU and jump to start_secondary */
> li r4,MSR_KERNEL
> @@ -942,6 +945,9 @@ start_here:
> li r3,0
> stw r3, RTAS_SP(r4) /* 0 => not in RTAS */
> #endif
> + lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
> + ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
> + mtspr SPRN_SPRG_PGDIR, r4
>
> /* stack */
> lis r1,init_thread_union@ha
> diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S
> index 1f13494efb2b..587e4550d83e 100644
> --- a/arch/powerpc/mm/hash_low_32.S
> +++ b/arch/powerpc/mm/hash_low_32.S
> @@ -70,12 +70,12 @@ _GLOBAL(hash_page)
> lis r0,KERNELBASE@h /* check if kernel address */
> cmplw 0,r4,r0
> ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
> - mfspr r5, SPRN_SPRG_PGDIR /* virt page-table root */
> + mfspr r5, SPRN_SPRG_PGDIR /* phys page-table root */
> blt+ 112f /* assume user more likely */
> - lis r5,swapper_pg_dir@ha /* if kernel address, use */
> - addi r5,r5,swapper_pg_dir@l /* kernel page table */
> + lis r5, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
> + addi r5 ,r5 , (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
> rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
> -112: tophys(r5, r5)
> +112:
> #ifndef CONFIG_PTE_64BIT
> rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
> lwz r8,0(r5) /* get pmd entry */
>
>
> Thanks
> Christophe
>
> >
> >Unfortunately, it is not possible to revert the patch due to subsequent
> >patches, so I was unable to test a revert.
> >
> >Bisect log is attached.
> >
> >Guenter
> >
> >---
> ># bad: [cf08baa29613dd899954089e7cc7dba1d478b365] Add linux-next specific files for 20190306
> ># good: [1c163f4c7b3f621efff9b28a47abb36f7378d783] Linux 5.0
> >git bisect start 'HEAD' 'v5.0'
> ># bad: [6cc8f3499ec8d31904ab9083980a91736512cb37] Merge remote-tracking branch 'vfs/for-next'
> >git bisect bad 6cc8f3499ec8d31904ab9083980a91736512cb37
> ># good: [63bdf4284c38a48af21745ceb148a087b190cd21] Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
> >git bisect good 63bdf4284c38a48af21745ceb148a087b190cd21
> ># good: [520b5fc601ab760fee7ea0c403b42d04e8ebfd93] Merge remote-tracking branch 'arm-soc/for-next'
> >git bisect good 520b5fc601ab760fee7ea0c403b42d04e8ebfd93
> ># bad: [d7f54e4e0d4e90f5df78da8d6a830bafad3b535a] Merge remote-tracking branch 'xtensa/xtensa-for-next'
> >git bisect bad d7f54e4e0d4e90f5df78da8d6a830bafad3b535a
> ># good: [0c1a78523542fb3d2e6c5ac7955c8ca8f6482e6f] Merge remote-tracking branch 'clk/clk-next'
> >git bisect good 0c1a78523542fb3d2e6c5ac7955c8ca8f6482e6f
> ># bad: [fb0b0a73b223fc113e961b1d921322844e9c30d9] powerpc: Enable kcov
> >git bisect bad fb0b0a73b223fc113e961b1d921322844e9c30d9
> ># good: [d0055df0c9c1471c389197a69f43e300185a75aa] Merge branch 'topic/dma' into next
> >git bisect good d0055df0c9c1471c389197a69f43e300185a75aa
> ># good: [0df977eafc792a5365a7f81d8d5920132e03afad] powerpc/6xx: Don't use SPRN_SPRG2 for storing stack pointer while in RTAS
> >git bisect good 0df977eafc792a5365a7f81d8d5920132e03afad
> ># bad: [665bed2386e5dc29844ad78c7ef1464664b103ec] powerpc/8xx: replace most #ifdef by IS_ENABLED() in 8xx_mmu.c
> >git bisect bad 665bed2386e5dc29844ad78c7ef1464664b103ec
> ># bad: [78ca1108b10927b3d068c8da91352b0f4cd01fc5] powerpc/book3s32: Reorder _PAGE_XXX flags to simplify TLB handling
> >git bisect bad 78ca1108b10927b3d068c8da91352b0f4cd01fc5
> ># bad: [a8a121995b2e4f227fddc534c6bd5f1c02cbe2ee] powerpc/603: Don't handle kernel page TLB misses when not need
> >git bisect bad a8a121995b2e4f227fddc534c6bd5f1c02cbe2ee
> ># bad: [2c12393f577396a51b7e0537bd3eb29dcc26dc1b] powerpc/603: use physical address directly in TLB miss handlers.
> >git bisect bad 2c12393f577396a51b7e0537bd3eb29dcc26dc1b
> ># bad: [93c4a162b014d238a287f8264adb25c009c79e61] powerpc/6xx: Store PGDIR physical address in a SPRG
> >git bisect bad 93c4a162b014d238a287f8264adb25c009c79e61
> ># first bad commit: [93c4a162b014d238a287f8264adb25c009c79e61] powerpc/6xx: Store PGDIR physical address in a SPRG
> >
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 03/10] powerpc/6xx: Store PGDIR physical address in a SPRG
2019-03-07 19:07 ` Guenter Roeck
@ 2019-03-07 19:10 ` Christophe Leroy
0 siblings, 0 replies; 16+ messages in thread
From: Christophe Leroy @ 2019-03-07 19:10 UTC (permalink / raw)
To: Guenter Roeck, Michael Ellerman
Cc: linuxppc-dev, Paul Mackerras, linux-kernel
Le 07/03/2019 à 20:07, Guenter Roeck a écrit :
> On Thu, Mar 07, 2019 at 06:14:09PM +0000, Christophe Leroy wrote:
>> Hi,
>>
>> On 03/07/2019 02:11 PM, Guenter Roeck wrote:
>>> Hi,
>>>
>>> On Thu, Feb 21, 2019 at 10:37:55AM +0000, Christophe Leroy wrote:
>>>> Use SPRN_SPRG2 to store the current thread PGDIR and
>>>> avoid reading thread_struct.pgdir at every TLB miss.
>>>>
>>> This patch causes a number of silent (no crash) qemu boot stalls
>>> in -next. See
>>> https://kerneltests.org/builders/qemu-ppc-next/builds/1080/steps/qemubuildcommand/logs/stdio
>>> for an example.
>>
>> Oops.
>> Could you try the fix below ?
>>
>
> Yes, that does the trick. With this patch applied on top of next-20190306,
> all my ppc qemu boot tests pass.
>
> Tested-by: Guenter Roeck <linux@roeck-us.net>
Thanks for testing.
I'll send a proper patch tomorrow morning, sorry for that.
Christophe
>
> Guenter
>
>> diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S
>> b/arch/powerpc/kernel/cpu_setup_6xx.S
>> index 6f1c11e0691f..7534ecff5e92 100644
>> --- a/arch/powerpc/kernel/cpu_setup_6xx.S
>> +++ b/arch/powerpc/kernel/cpu_setup_6xx.S
>> @@ -24,9 +24,6 @@ BEGIN_MMU_FTR_SECTION
>> li r10,0
>> mtspr SPRN_SPRG_603_LRU,r10 /* init SW LRU tracking */
>> END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
>> - lis r10, (swapper_pg_dir - PAGE_OFFSET)@h
>> - ori r10, r10, (swapper_pg_dir - PAGE_OFFSET)@l
>> - mtspr SPRN_SPRG_PGDIR, r10
>>
>> BEGIN_FTR_SECTION
>> bl __init_fpu_registers
>> diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
>> index ce6a972f2584..48051c8977c5 100644
>> --- a/arch/powerpc/kernel/head_32.S
>> +++ b/arch/powerpc/kernel/head_32.S
>> @@ -855,6 +855,9 @@ __secondary_start:
>> li r3,0
>> stw r3, RTAS_SP(r4) /* 0 => not in RTAS */
>> #endif
>> + lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
>> + ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
>> + mtspr SPRN_SPRG_PGDIR, r4
>>
>> /* enable MMU and jump to start_secondary */
>> li r4,MSR_KERNEL
>> @@ -942,6 +945,9 @@ start_here:
>> li r3,0
>> stw r3, RTAS_SP(r4) /* 0 => not in RTAS */
>> #endif
>> + lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
>> + ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
>> + mtspr SPRN_SPRG_PGDIR, r4
>>
>> /* stack */
>> lis r1,init_thread_union@ha
>> diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S
>> index 1f13494efb2b..587e4550d83e 100644
>> --- a/arch/powerpc/mm/hash_low_32.S
>> +++ b/arch/powerpc/mm/hash_low_32.S
>> @@ -70,12 +70,12 @@ _GLOBAL(hash_page)
>> lis r0,KERNELBASE@h /* check if kernel address */
>> cmplw 0,r4,r0
>> ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
>> - mfspr r5, SPRN_SPRG_PGDIR /* virt page-table root */
>> + mfspr r5, SPRN_SPRG_PGDIR /* phys page-table root */
>> blt+ 112f /* assume user more likely */
>> - lis r5,swapper_pg_dir@ha /* if kernel address, use */
>> - addi r5,r5,swapper_pg_dir@l /* kernel page table */
>> + lis r5, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
>> + addi r5 ,r5 , (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
>> rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
>> -112: tophys(r5, r5)
>> +112:
>> #ifndef CONFIG_PTE_64BIT
>> rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
>> lwz r8,0(r5) /* get pmd entry */
>>
>>
>> Thanks
>> Christophe
>>
>>>
>>> Unfortunately, it is not possible to revert the patch due to subsequent
>>> patches, so I was unable to test a revert.
>>>
>>> Bisect log is attached.
>>>
>>> Guenter
>>>
>>> ---
>>> # bad: [cf08baa29613dd899954089e7cc7dba1d478b365] Add linux-next specific files for 20190306
>>> # good: [1c163f4c7b3f621efff9b28a47abb36f7378d783] Linux 5.0
>>> git bisect start 'HEAD' 'v5.0'
>>> # bad: [6cc8f3499ec8d31904ab9083980a91736512cb37] Merge remote-tracking branch 'vfs/for-next'
>>> git bisect bad 6cc8f3499ec8d31904ab9083980a91736512cb37
>>> # good: [63bdf4284c38a48af21745ceb148a087b190cd21] Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
>>> git bisect good 63bdf4284c38a48af21745ceb148a087b190cd21
>>> # good: [520b5fc601ab760fee7ea0c403b42d04e8ebfd93] Merge remote-tracking branch 'arm-soc/for-next'
>>> git bisect good 520b5fc601ab760fee7ea0c403b42d04e8ebfd93
>>> # bad: [d7f54e4e0d4e90f5df78da8d6a830bafad3b535a] Merge remote-tracking branch 'xtensa/xtensa-for-next'
>>> git bisect bad d7f54e4e0d4e90f5df78da8d6a830bafad3b535a
>>> # good: [0c1a78523542fb3d2e6c5ac7955c8ca8f6482e6f] Merge remote-tracking branch 'clk/clk-next'
>>> git bisect good 0c1a78523542fb3d2e6c5ac7955c8ca8f6482e6f
>>> # bad: [fb0b0a73b223fc113e961b1d921322844e9c30d9] powerpc: Enable kcov
>>> git bisect bad fb0b0a73b223fc113e961b1d921322844e9c30d9
>>> # good: [d0055df0c9c1471c389197a69f43e300185a75aa] Merge branch 'topic/dma' into next
>>> git bisect good d0055df0c9c1471c389197a69f43e300185a75aa
>>> # good: [0df977eafc792a5365a7f81d8d5920132e03afad] powerpc/6xx: Don't use SPRN_SPRG2 for storing stack pointer while in RTAS
>>> git bisect good 0df977eafc792a5365a7f81d8d5920132e03afad
>>> # bad: [665bed2386e5dc29844ad78c7ef1464664b103ec] powerpc/8xx: replace most #ifdef by IS_ENABLED() in 8xx_mmu.c
>>> git bisect bad 665bed2386e5dc29844ad78c7ef1464664b103ec
>>> # bad: [78ca1108b10927b3d068c8da91352b0f4cd01fc5] powerpc/book3s32: Reorder _PAGE_XXX flags to simplify TLB handling
>>> git bisect bad 78ca1108b10927b3d068c8da91352b0f4cd01fc5
>>> # bad: [a8a121995b2e4f227fddc534c6bd5f1c02cbe2ee] powerpc/603: Don't handle kernel page TLB misses when not need
>>> git bisect bad a8a121995b2e4f227fddc534c6bd5f1c02cbe2ee
>>> # bad: [2c12393f577396a51b7e0537bd3eb29dcc26dc1b] powerpc/603: use physical address directly in TLB miss handlers.
>>> git bisect bad 2c12393f577396a51b7e0537bd3eb29dcc26dc1b
>>> # bad: [93c4a162b014d238a287f8264adb25c009c79e61] powerpc/6xx: Store PGDIR physical address in a SPRG
>>> git bisect bad 93c4a162b014d238a287f8264adb25c009c79e61
>>> # first bad commit: [93c4a162b014d238a287f8264adb25c009c79e61] powerpc/6xx: Store PGDIR physical address in a SPRG
>>>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 04/10] powerpc/603: use physical address directly in TLB miss handlers.
2019-02-21 10:37 [PATCH v2 00/10] Optimise TLB miss handlers on 6xx (603/e300) Christophe Leroy
` (2 preceding siblings ...)
2019-02-21 10:37 ` [PATCH v2 03/10] powerpc/6xx: Store PGDIR physical address in a SPRG Christophe Leroy
@ 2019-02-21 10:37 ` Christophe Leroy
2019-02-21 10:37 ` [PATCH v2 05/10] powerpc/hash32: use physical address directly in hash handlers Christophe Leroy
` (5 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Christophe Leroy @ 2019-02-21 10:37 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
Since commit c62ce9ef97ba ("powerpc: remove remaining bits from
CONFIG_APUS"), tophys() has become a pure constant operation.
PAGE_OFFSET is known at compile time so the physical address
can be builtin directly.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/kernel/head_32.S | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 2b0a26f66115..4c2cc42399aa 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -505,9 +505,8 @@ InstructionTLBMiss:
bge- 112f
mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
- lis r2,swapper_pg_dir@ha /* if kernel address, use */
- addi r2,r2,swapper_pg_dir@l /* kernel page table */
- tophys(r2,r2)
+ lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
+ addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
lwz r2,0(r2) /* get pmd entry */
rlwinm. r2,r2,0,0,19 /* extract address of pte page */
@@ -578,9 +577,8 @@ DataLoadTLBMiss:
bge- 112f
mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
- lis r2,swapper_pg_dir@ha /* if kernel address, use */
- addi r2,r2,swapper_pg_dir@l /* kernel page table */
- tophys(r2,r2)
+ lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
+ addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
lwz r2,0(r2) /* get pmd entry */
rlwinm. r2,r2,0,0,19 /* extract address of pte page */
@@ -661,9 +659,8 @@ DataStoreTLBMiss:
bge- 112f
mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
- lis r2,swapper_pg_dir@ha /* if kernel address, use */
- addi r2,r2,swapper_pg_dir@l /* kernel page table */
- tophys(r2,r2)
+ lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
+ addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
lwz r2,0(r2) /* get pmd entry */
rlwinm. r2,r2,0,0,19 /* extract address of pte page */
--
2.13.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 05/10] powerpc/hash32: use physical address directly in hash handlers.
2019-02-21 10:37 [PATCH v2 00/10] Optimise TLB miss handlers on 6xx (603/e300) Christophe Leroy
` (3 preceding siblings ...)
2019-02-21 10:37 ` [PATCH v2 04/10] powerpc/603: use physical address directly in TLB miss handlers Christophe Leroy
@ 2019-02-21 10:37 ` Christophe Leroy
2019-02-21 10:37 ` [PATCH v2 06/10] powerpc/603: Don't handle kernel page TLB misses when not need Christophe Leroy
` (4 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Christophe Leroy @ 2019-02-21 10:37 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
Since commit c62ce9ef97ba ("powerpc: remove remaining bits from
CONFIG_APUS"), tophys() has become a pure constant operation.
PAGE_OFFSET is known at compile time so the physical address
can be builtin directly.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/mm/hash_low_32.S | 62 +++++++++++++++++++------------------------
arch/powerpc/mm/ppc_mmu_32.c | 6 +++--
2 files changed, 31 insertions(+), 37 deletions(-)
diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S
index 82e7dd0c0220..d94fef524ef5 100644
--- a/arch/powerpc/mm/hash_low_32.S
+++ b/arch/powerpc/mm/hash_low_32.S
@@ -47,14 +47,13 @@ mmu_hash_lock:
* Returns to the caller if the access is illegal or there is no
* mapping for the address. Otherwise it places an appropriate PTE
* in the hash table and returns from the exception.
- * Uses r0, r3 - r8, r10, ctr, lr.
+ * Uses r0, r3 - r6, r8, r10, ctr, lr.
*/
.text
_GLOBAL(hash_page)
- tophys(r7,0) /* gets -KERNELBASE into r7 */
#ifdef CONFIG_SMP
- addis r8,r7,mmu_hash_lock@h
- ori r8,r8,mmu_hash_lock@l
+ lis r8, (mmu_hash_lock - PAGE_OFFSET)@h
+ ori r8, r8, (mmu_hash_lock - PAGE_OFFSET)@l
lis r0,0x0fff
b 10f
11: lwz r6,0(r8)
@@ -76,7 +75,7 @@ _GLOBAL(hash_page)
lis r5,swapper_pg_dir@ha /* if kernel address, use */
addi r5,r5,swapper_pg_dir@l /* kernel page table */
rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
-112: add r5,r5,r7 /* convert to phys addr */
+112: tophys(r5, r5)
#ifndef CONFIG_PTE_64BIT
rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
lwz r8,0(r5) /* get pmd entry */
@@ -143,25 +142,24 @@ retry:
#ifdef CONFIG_SMP
eieio
- addis r8,r7,mmu_hash_lock@ha
+ lis r8, (mmu_hash_lock - PAGE_OFFSET)@ha
li r0,0
- stw r0,mmu_hash_lock@l(r8)
+ stw r0, (mmu_hash_lock - PAGE_OFFSET)@l(r8)
#endif
/* Return from the exception */
lwz r5,_CTR(r11)
mtctr r5
lwz r0,GPR0(r11)
- lwz r7,GPR7(r11)
lwz r8,GPR8(r11)
b fast_exception_return
#ifdef CONFIG_SMP
hash_page_out:
eieio
- addis r8,r7,mmu_hash_lock@ha
+ lis r8, (mmu_hash_lock - PAGE_OFFSET)@ha
li r0,0
- stw r0,mmu_hash_lock@l(r8)
+ stw r0, (mmu_hash_lock - PAGE_OFFSET)@l(r8)
blr
#endif /* CONFIG_SMP */
@@ -207,11 +205,9 @@ _GLOBAL(add_hash_page)
SYNC_601
isync
- tophys(r7,0)
-
#ifdef CONFIG_SMP
- addis r6,r7,mmu_hash_lock@ha
- addi r6,r6,mmu_hash_lock@l
+ lis r6, (mmu_hash_lock - PAGE_OFFSET)@ha
+ addi r6, r6, (mmu_hash_lock - PAGE_OFFSET)@l
10: lwarx r0,0,r6 /* take the mmu_hash_lock */
cmpi 0,r0,0
bne- 11f
@@ -256,8 +252,8 @@ _GLOBAL(add_hash_page)
9:
#ifdef CONFIG_SMP
- addis r6,r7,mmu_hash_lock@ha
- addi r6,r6,mmu_hash_lock@l
+ lis r6, (mmu_hash_lock - PAGE_OFFSET)@ha
+ addi r6, r6, (mmu_hash_lock - PAGE_OFFSET)@l
eieio
li r0,0
stw r0,0(r6) /* clear mmu_hash_lock */
@@ -277,10 +273,8 @@ _GLOBAL(add_hash_page)
* It is designed to be called with the MMU either on or off.
* r3 contains the VSID, r4 contains the virtual address,
* r5 contains the linux PTE, r6 contains the old value of the
- * linux PTE (before setting _PAGE_HASHPTE) and r7 contains the
- * offset to be added to addresses (0 if the MMU is on,
- * -KERNELBASE if it is off). r10 contains the upper half of
- * the PTE if CONFIG_PTE_64BIT.
+ * linux PTE (before setting _PAGE_HASHPTE). r10 contains the
+ * upper half of the PTE if CONFIG_PTE_64BIT.
* On SMP, the caller should have the mmu_hash_lock held.
* We assume that the caller has (or will) set the _PAGE_HASHPTE
* bit in the linux PTE in memory. The value passed in r6 should
@@ -341,7 +335,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
patch_site 1f, patch__hash_page_A1
patch_site 2f, patch__hash_page_A2
/* Get the address of the primary PTE group in the hash table (r3) */
-0: addis r0,r7,Hash_base@h /* base address of hash table */
+0: lis r0, (Hash_base - PAGE_OFFSET)@h /* base address of hash table */
1: rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
2: rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
xor r3,r3,r0 /* make primary hash */
@@ -355,10 +349,10 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
beq+ 10f /* no PTE: go look for an empty slot */
tlbie r4
- addis r4,r7,htab_hash_searches@ha
- lwz r6,htab_hash_searches@l(r4)
+ lis r4, (htab_hash_searches - PAGE_OFFSET)@ha
+ lwz r6, (htab_hash_searches - PAGE_OFFSET)@l(r4)
addi r6,r6,1 /* count how many searches we do */
- stw r6,htab_hash_searches@l(r4)
+ stw r6, (htab_hash_searches - PAGE_OFFSET)@l(r4)
/* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
mtctr r0
@@ -390,10 +384,10 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
beq+ found_empty
/* update counter of times that the primary PTEG is full */
- addis r4,r7,primary_pteg_full@ha
- lwz r6,primary_pteg_full@l(r4)
+ lis r4, (primary_pteg_full - PAGE_OFFSET)@ha
+ lwz r6, (primary_pteg_full - PAGE_OFFSET)@l(r4)
addi r6,r6,1
- stw r6,primary_pteg_full@l(r4)
+ stw r6, (primary_pteg_full - PAGE_OFFSET)@l(r4)
patch_site 0f, patch__hash_page_C
/* Search the secondary PTEG for an empty slot */
@@ -427,8 +421,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
* lockup here but that shouldn't happen
*/
-1: addis r4,r7,next_slot@ha /* get next evict slot */
- lwz r6,next_slot@l(r4)
+1: lis r4, (next_slot - PAGE_OFFSET)@ha /* get next evict slot */
+ lwz r6, (next_slot - PAGE_OFFSET)@l(r4)
addi r6,r6,HPTE_SIZE /* search for candidate */
andi. r6,r6,7*HPTE_SIZE
stw r6,next_slot@l(r4)
@@ -500,8 +494,6 @@ htab_hash_searches:
* We assume that there is a hash table in use (Hash != 0).
*/
_GLOBAL(flush_hash_pages)
- tophys(r7,0)
-
/*
* We disable interrupts here, even on UP, because we want
* the _PAGE_HASHPTE bit to be a reliable indication of
@@ -546,10 +538,10 @@ _GLOBAL(flush_hash_pages)
SET_V(r11) /* set V (valid) bit */
#ifdef CONFIG_SMP
- addis r9,r7,mmu_hash_lock@ha
- addi r9,r9,mmu_hash_lock@l
+ lis r9, (mmu_hash_lock - PAGE_OFFSET)@ha
+ addi r9, r9, (mmu_hash_lock - PAGE_OFFSET)@l
CURRENT_THREAD_INFO(r8, r1)
- add r8,r8,r7
+ tophys(r8, r8)
lwz r8,TI_CPU(r8)
oris r8,r8,9
10: lwarx r0,0,r9
@@ -583,7 +575,7 @@ _GLOBAL(flush_hash_pages)
patch_site 1f, patch__flush_hash_A1
patch_site 2f, patch__flush_hash_A2
/* Get the address of the primary PTE group in the hash table (r3) */
-0: addis r8,r7,Hash_base@h /* base address of hash table */
+0: lis r8, (Hash_base - PAGE_OFFSET)@h /* base address of hash table */
1: rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
2: rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
xor r8,r0,r8 /* make primary hash */
diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c
index 3f4193201ee7..fb747bb0b3e4 100644
--- a/arch/powerpc/mm/ppc_mmu_32.c
+++ b/arch/powerpc/mm/ppc_mmu_32.c
@@ -231,7 +231,8 @@ void __init MMU_init_hw(void)
if (lg_n_hpteg > 16)
mb2 = 16 - LG_HPTEG_SIZE;
- modify_instruction_site(&patch__hash_page_A0, 0xffff, (unsigned int)Hash >> 16);
+ modify_instruction_site(&patch__hash_page_A0, 0xffff,
+ ((unsigned int)Hash - PAGE_OFFSET) >> 16);
modify_instruction_site(&patch__hash_page_A1, 0x7c0, mb << 6);
modify_instruction_site(&patch__hash_page_A2, 0x7c0, mb2 << 6);
modify_instruction_site(&patch__hash_page_B, 0xffff, hmask);
@@ -240,7 +241,8 @@ void __init MMU_init_hw(void)
/*
* Patch up the instructions in hashtable.S:flush_hash_page
*/
- modify_instruction_site(&patch__flush_hash_A0, 0xffff, (unsigned int)Hash >> 16);
+ modify_instruction_site(&patch__flush_hash_A0, 0xffff,
+ ((unsigned int)Hash - PAGE_OFFSET) >> 16);
modify_instruction_site(&patch__flush_hash_A1, 0x7c0, mb << 6);
modify_instruction_site(&patch__flush_hash_A2, 0x7c0, mb2 << 6);
modify_instruction_site(&patch__flush_hash_B, 0xffff, hmask);
--
2.13.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 06/10] powerpc/603: Don't handle kernel page TLB misses when not need
2019-02-21 10:37 [PATCH v2 00/10] Optimise TLB miss handlers on 6xx (603/e300) Christophe Leroy
` (4 preceding siblings ...)
2019-02-21 10:37 ` [PATCH v2 05/10] powerpc/hash32: use physical address directly in hash handlers Christophe Leroy
@ 2019-02-21 10:37 ` Christophe Leroy
2019-02-21 10:37 ` [PATCH v2 07/10] powerpc/603: Don't handle _PAGE_RW and _PAGE_DIRTY on ITLB misses Christophe Leroy
` (3 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Christophe Leroy @ 2019-02-21 10:37 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
ITLB miss on kernel pages only occur with CONFIG_MODULES and
CONFIG_DEBUG_PAGEALLOC.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/kernel/head_32.S | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 4c2cc42399aa..e4338d785a94 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -498,15 +498,19 @@ InstructionTLBMiss:
*/
/* Get PTE (linux-style) and check access */
mfspr r3,SPRN_IMISS
+#if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
lis r1,PAGE_OFFSET@h /* check if kernel address */
cmplw 0,r1,r3
+#endif
mfspr r2, SPRN_SPRG_PGDIR
li r1,_PAGE_USER|_PAGE_PRESENT|_PAGE_EXEC /* low addresses tested as user */
+#if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
bge- 112f
mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
+#endif
112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
lwz r2,0(r2) /* get pmd entry */
rlwinm. r2,r2,0,0,19 /* extract address of pte page */
--
2.13.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 07/10] powerpc/603: Don't handle _PAGE_RW and _PAGE_DIRTY on ITLB misses
2019-02-21 10:37 [PATCH v2 00/10] Optimise TLB miss handlers on 6xx (603/e300) Christophe Leroy
` (5 preceding siblings ...)
2019-02-21 10:37 ` [PATCH v2 06/10] powerpc/603: Don't handle kernel page TLB misses when not need Christophe Leroy
@ 2019-02-21 10:37 ` Christophe Leroy
2019-02-21 10:38 ` [PATCH v2 08/10] powerpc/603: let's handle PAGE_DIRTY directly Christophe Leroy
` (2 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Christophe Leroy @ 2019-02-21 10:37 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
_PAGE_RW and _PAGE_DIRTY do not matter for ITLB misses.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/kernel/head_32.S | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index e4338d785a94..6db54425f1d9 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -526,13 +526,9 @@ InstructionTLBMiss:
*/
stw r0,0(r2) /* update PTE (accessed bit) */
/* Convert linux-style PTE to low word of PPC-style PTE */
- rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */
- rlwinm r2,r0,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
- and r1,r1,r2 /* writable if _RW and _DIRTY */
rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
- rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
- ori r1,r1,0xe04 /* clear out reserved bits */
- andc r1,r0,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
+ ori r1, r1, 0xe05 /* clear out reserved bits */
+ andc r1, r0, r1 /* PP = user? 2 : 0 */
BEGIN_FTR_SECTION
rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
--
2.13.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 08/10] powerpc/603: let's handle PAGE_DIRTY directly
2019-02-21 10:37 [PATCH v2 00/10] Optimise TLB miss handlers on 6xx (603/e300) Christophe Leroy
` (6 preceding siblings ...)
2019-02-21 10:37 ` [PATCH v2 07/10] powerpc/603: Don't handle _PAGE_RW and _PAGE_DIRTY on ITLB misses Christophe Leroy
@ 2019-02-21 10:38 ` Christophe Leroy
2019-02-21 10:38 ` [PATCH v2 09/10] powerpc/603: Don't worry about _PAGE_USER in TLB miss handlers Christophe Leroy
2019-02-21 10:38 ` [PATCH v2 10/10] powerpc/603: don't handle PAGE_ACCESSED " Christophe Leroy
9 siblings, 0 replies; 16+ messages in thread
From: Christophe Leroy @ 2019-02-21 10:38 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
PAGE_DIRTY corresponds to the C bit. If writing on
a page for which the C bit is not set, a DataStoreTLBMiss
is generated. No need to check it in DataLoadTLBMiss.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/kernel/head_32.S | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 6db54425f1d9..b071f328b4b0 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -595,12 +595,10 @@ DataLoadTLBMiss:
stw r0,0(r2) /* update PTE (accessed bit) */
/* Convert linux-style PTE to low word of PPC-style PTE */
rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */
- rlwinm r2,r0,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
- and r1,r1,r2 /* writable if _RW and _DIRTY */
rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
ori r1,r1,0xe04 /* clear out reserved bits */
- andc r1,r0,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
+ andc r1,r0,r1 /* PP = user? rw? 2: 3: 0 */
BEGIN_FTR_SECTION
rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
@@ -669,7 +667,7 @@ DataStoreTLBMiss:
lwz r0,0(r2) /* get linux-style pte */
andc. r1,r1,r0 /* check access & ~permission */
bne- DataAddressInvalid /* return if access not permitted */
- ori r0,r0,_PAGE_ACCESSED|_PAGE_DIRTY
+ ori r0,r0,_PAGE_ACCESSED
/*
* NOTE! We are assuming this is not an SMP system, otherwise
* we would need to update the pte atomically with lwarx/stwcx.
--
2.13.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 09/10] powerpc/603: Don't worry about _PAGE_USER in TLB miss handlers
2019-02-21 10:37 [PATCH v2 00/10] Optimise TLB miss handlers on 6xx (603/e300) Christophe Leroy
` (7 preceding siblings ...)
2019-02-21 10:38 ` [PATCH v2 08/10] powerpc/603: let's handle PAGE_DIRTY directly Christophe Leroy
@ 2019-02-21 10:38 ` Christophe Leroy
2019-02-21 10:38 ` [PATCH v2 10/10] powerpc/603: don't handle PAGE_ACCESSED " Christophe Leroy
9 siblings, 0 replies; 16+ messages in thread
From: Christophe Leroy @ 2019-02-21 10:38 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
PP bits take user access into account, so no need to check _PAGE_USER
here. A DSI or ISI will be generated if needed.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/kernel/head_32.S | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index b071f328b4b0..6b5cb7551a72 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -503,11 +503,9 @@ InstructionTLBMiss:
cmplw 0,r1,r3
#endif
mfspr r2, SPRN_SPRG_PGDIR
- li r1,_PAGE_USER|_PAGE_PRESENT|_PAGE_EXEC /* low addresses tested as user */
+ li r1,_PAGE_PRESENT | _PAGE_EXEC
#if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
bge- 112f
- mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
- rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
#endif
@@ -573,10 +571,8 @@ DataLoadTLBMiss:
lis r1,PAGE_OFFSET@h /* check if kernel address */
cmplw 0,r1,r3
mfspr r2, SPRN_SPRG_PGDIR
- li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
+ li r1, _PAGE_PRESENT
bge- 112f
- mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
- rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
@@ -653,10 +649,8 @@ DataStoreTLBMiss:
lis r1,PAGE_OFFSET@h /* check if kernel address */
cmplw 0,r1,r3
mfspr r2, SPRN_SPRG_PGDIR
- li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
+ li r1, _PAGE_RW | _PAGE_PRESENT /* access flags */
bge- 112f
- mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
- rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
--
2.13.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 10/10] powerpc/603: don't handle PAGE_ACCESSED in TLB miss handlers.
2019-02-21 10:37 [PATCH v2 00/10] Optimise TLB miss handlers on 6xx (603/e300) Christophe Leroy
` (8 preceding siblings ...)
2019-02-21 10:38 ` [PATCH v2 09/10] powerpc/603: Don't worry about _PAGE_USER in TLB miss handlers Christophe Leroy
@ 2019-02-21 10:38 ` Christophe Leroy
9 siblings, 0 replies; 16+ messages in thread
From: Christophe Leroy @ 2019-02-21 10:38 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
PAGE_ACCESSED is only needed for CONFIG_SWAP. When CONFIG_SWAP
is not set, just ignore it. If CONFIG_SWAP is set and PAGE_ACCESSED
is not, let's take a minor fault.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/kernel/head_32.S | 24 +++++++++++++-----------
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 6b5cb7551a72..fdb587c96a80 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -503,7 +503,11 @@ InstructionTLBMiss:
cmplw 0,r1,r3
#endif
mfspr r2, SPRN_SPRG_PGDIR
+#ifdef CONFIG_SWAP
+ li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
+#else
li r1,_PAGE_PRESENT | _PAGE_EXEC
+#endif
#if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
bge- 112f
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
@@ -517,12 +521,6 @@ InstructionTLBMiss:
lwz r0,0(r2) /* get linux-style pte */
andc. r1,r1,r0 /* check access & ~permission */
bne- InstructionAddressInvalid /* return if access not permitted */
- ori r0,r0,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
- /*
- * NOTE! We are assuming this is not an SMP system, otherwise
- * we would need to update the pte atomically with lwarx/stwcx.
- */
- stw r0,0(r2) /* update PTE (accessed bit) */
/* Convert linux-style PTE to low word of PPC-style PTE */
rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
ori r1, r1, 0xe05 /* clear out reserved bits */
@@ -571,7 +569,11 @@ DataLoadTLBMiss:
lis r1,PAGE_OFFSET@h /* check if kernel address */
cmplw 0,r1,r3
mfspr r2, SPRN_SPRG_PGDIR
+#ifdef CONFIG_SWAP
+ li r1, _PAGE_PRESENT | _PAGE_ACCESSED
+#else
li r1, _PAGE_PRESENT
+#endif
bge- 112f
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
@@ -583,12 +585,10 @@ DataLoadTLBMiss:
lwz r0,0(r2) /* get linux-style pte */
andc. r1,r1,r0 /* check access & ~permission */
bne- DataAddressInvalid /* return if access not permitted */
- ori r0,r0,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
/*
* NOTE! We are assuming this is not an SMP system, otherwise
* we would need to update the pte atomically with lwarx/stwcx.
*/
- stw r0,0(r2) /* update PTE (accessed bit) */
/* Convert linux-style PTE to low word of PPC-style PTE */
rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */
rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
@@ -649,7 +649,11 @@ DataStoreTLBMiss:
lis r1,PAGE_OFFSET@h /* check if kernel address */
cmplw 0,r1,r3
mfspr r2, SPRN_SPRG_PGDIR
- li r1, _PAGE_RW | _PAGE_PRESENT /* access flags */
+#ifdef CONFIG_SWAP
+ li r1, _PAGE_RW | _PAGE_PRESENT | _PAGE_ACCESSED
+#else
+ li r1, _PAGE_RW | _PAGE_PRESENT
+#endif
bge- 112f
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
@@ -661,12 +665,10 @@ DataStoreTLBMiss:
lwz r0,0(r2) /* get linux-style pte */
andc. r1,r1,r0 /* check access & ~permission */
bne- DataAddressInvalid /* return if access not permitted */
- ori r0,r0,_PAGE_ACCESSED
/*
* NOTE! We are assuming this is not an SMP system, otherwise
* we would need to update the pte atomically with lwarx/stwcx.
*/
- stw r0,0(r2) /* update PTE (accessed/dirty bits) */
/* Convert linux-style PTE to low word of PPC-style PTE */
rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
li r1,0xe05 /* clear out reserved bits & PP lsb */
--
2.13.3
^ permalink raw reply related [flat|nested] 16+ messages in thread