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Wed, 12 Aug 2020 06:43:30 +0000 (GMT) Received: from [9.85.71.109] (unknown [9.85.71.109]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 12 Aug 2020 06:43:30 +0000 (GMT) Subject: Re: [PATCH 02/16] debug_vm_pgtable/ppc64: Avoid setting top bits in radom value To: Christophe Leroy , linux-mm@kvack.org, akpm@linux-foundation.org References: <20200812063358.369514-1-aneesh.kumar@linux.ibm.com> <20200812063358.369514-2-aneesh.kumar@linux.ibm.com> <24b1e523-e87e-161b-3dc9-60bd11c8f461@csgroup.eu> From: "Aneesh Kumar K.V" Message-ID: Date: Wed, 12 Aug 2020 12:13:29 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <24b1e523-e87e-161b-3dc9-60bd11c8f461@csgroup.eu> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-11_19:2020-08-11, 2020-08-11 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 malwarescore=0 adultscore=0 mlxscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=980 impostorscore=0 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008120047 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, Anshuman Khandual Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 8/12/20 12:10 PM, Christophe Leroy wrote: > > > Le 12/08/2020 à 08:33, Aneesh Kumar K.V a écrit : >> ppc64 use bit 62 to indicate a pte entry (_PAGE_PTE). Avoid setting >> that bit in >> random value. >> >> Signed-off-by: Aneesh Kumar K.V >> --- >>   mm/debug_vm_pgtable.c | 5 ++++- >>   1 file changed, 4 insertions(+), 1 deletion(-) >> >> diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c >> index 086309fb9b6f..4c32063a8acf 100644 >> --- a/mm/debug_vm_pgtable.c >> +++ b/mm/debug_vm_pgtable.c >> @@ -45,9 +45,12 @@ >>    * pxx_clear() because of how dynamic page table folding works on >> s390. So >>    * while loading up the entries do not change the lower 4 bits. It >> does not >>    * have affect any other platform. >> + * >> + * Also avoid the 62nd bit on ppc64 that is used to mark a pte entry. >>    */ >>   #define S390_MASK_BITS    4 >> -#define RANDOM_ORVALUE    GENMASK(BITS_PER_LONG - 1, S390_MASK_BITS) >> +#define PPC_MASK_BITS    2 >> +#define RANDOM_ORVALUE    GENMASK(BITS_PER_LONG - 1 - PPC_MASK_BITS, >> S390_MASK_BITS) > > Do you mean: > > #define RANDOM_ORVALUE    GENMASK(BITS_PER_LONG - 1, PPC_MASK_BITS | > S390_MASK_BITS) IIUC GENMASK(hi, low) generate a mask from hi to low bits. Since i want to avoid bit 62, I am forcing it to generate bits from (61, 4) -aneesh