From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from penguin.netx4.com (embeddededge.com [209.113.146.155]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTP id 3FE8C679E1 for ; Thu, 9 Jun 2005 02:12:07 +1000 (EST) In-Reply-To: <20050608102938.023f271f.ajz@cambridgebroadband.com> References: <20050608102938.023f271f.ajz@cambridgebroadband.com> Mime-Version: 1.0 (Apple Message framework v622) Content-Type: text/plain; charset=US-ASCII; format=flowed Message-Id: From: Dan Malek Date: Wed, 8 Jun 2005 12:12:01 -0400 To: Alex Zeffertt Cc: linuxppc-embedded@ozlabs.org Subject: Re: consistent_alloc() on 82xx List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Jun 8, 2005, at 5:29 AM, Alex Zeffertt wrote: > Does anybody know why it isn't built for 6xx cores? Because 6xx cores are cache coherent and there shouldn't be any need for "uncached" memory regions. > I'm working on the ATM driver and it seems that certain external memory > areas accessed by the PQII CPM by-pass the cache. That's news to me, and I've written lots of CPM drivers, including ATM. Do you have a specific example? Thanks. -- Dan