Hi Stefan,
Also in the SETUP stage where I have set my packet size as 1, as I treat
each of this 3 stages (SETUP, DATA and STATUS) as three different
stages/transactions, I find that the "Non-Periodic Transmit FIFO/Queue
Status Register" read as soon as I write to the "Non-Periodic Transmit
FIFO Size Register" as "0x10500fa". Before writing the value is
"0x80100". Is it fine that the bit 7 which defines the termination
of channel a right thing to happen?
Secondly since i am writing 2 bytes to the FIFO why should the "Non-periodic TxFIFO Space Avail (NPTxFSpcAvail)" bits of USB0_GNPTXSTS be 0xfa?
The FIFO to which I write:
*USB0_GRXFSIZ - 0x213 USB0_GNPTXFSIZ - 0x1000213*
The above setting mean that my Non-Periodic Transmit register starts at
0x213. So I write my data (8 byte SETUP Token Data) in the following way:
- Write the first 4 bytes to the starting adress of 0x1000 since I
am using Channel 0 --- (*(volatile unsigned *)(DHc->base + 0x1000 +
(bEnd * 0x1000) + 0x213 + fifo_address_offset))=*((volatile
unsigned *)pSrcBuf);
- Then increment the "fifo_adress_offset" by 4 and write the next 4 bytes.
I think that there is some problem in the SETUP (Token) Stage. Can you
please pass any pointers over this?
Regards;
Aadish
Hi Stefan,
I am working on the internal OTG controller. The synopsys DWC.
Regards;
AadishOn Wed, Feb 25, 2009 at 5:57 PM, Stefan Roese <sr@denx.de> wrote:
Are you talking about the 405EX internal USB OTG controller (Synopsys DWC) orOn Wednesday 25 February 2009, Adish Kuvelker wrote:
> I am developing a Host Controller Driver for the PPC405EX based board. I
> have a OTG controller on it, which I have to configure as Host Controller
> and thus I am witting a HCD for the same. I am stuck at the Control stage
> wherein although my SETUP stage seems to be going through I get a STALL.
>
> Can anyone help me in this regard as to where would I get a reference code
> for this?
some other OTG controller?
Best regards,
Stefan