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Mon, 14 Mar 2022 15:15:56 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DA78011C6FC; Mon, 14 Mar 2022 15:15:55 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C198C11C6EC; Mon, 14 Mar 2022 15:15:55 +0000 (GMT) Received: from [9.101.4.33] (unknown [9.101.4.33]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 14 Mar 2022 15:15:55 +0000 (GMT) Message-ID: Date: Mon, 14 Mar 2022 16:15:55 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 05/14] powerpc/rtas: Modernise RI clearing on 64-bit Content-Language: en-US To: Nicholas Piggin , linuxppc-dev@lists.ozlabs.org References: <20220308135047.478297-1-npiggin@gmail.com> <20220308135047.478297-6-npiggin@gmail.com> From: Laurent Dufour In-Reply-To: <20220308135047.478297-6-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: JN0BI-kDguPVHp14I6DS51c6vIrRv59c X-Proofpoint-ORIG-GUID: hoSdD295DruoXrSTURRdnD4la7hHfbCv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-14_11,2022-03-14_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=895 impostorscore=0 adultscore=0 clxscore=1015 suspectscore=0 mlxscore=0 priorityscore=1501 bulkscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203140095 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 08/03/2022, 14:50:38, Nicholas Piggin wrote: > mtmsrd L=1 can clear MSR[RI] without the previous MSR value; it does > not require sync; it can be moved later to before SRRs are live. > > Signed-off-by: Nicholas Piggin Reviewed-by: Laurent Dufour > --- > arch/powerpc/kernel/rtas_entry.S | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/powerpc/kernel/rtas_entry.S b/arch/powerpc/kernel/rtas_entry.S > index 45fa661c2ff6..7b93687b9a10 100644 > --- a/arch/powerpc/kernel/rtas_entry.S > +++ b/arch/powerpc/kernel/rtas_entry.S > @@ -109,13 +109,13 @@ _GLOBAL(enter_rtas) > andc r6,r0,r9 > > __enter_rtas: > - sync /* disable RI so SRR0/1 */ > - mtmsrd r0 /* don't get trashed */ > - > LOAD_REG_ADDR(r4, rtas) > ld r5,RTASENTRY(r4) /* get the rtas->entry value */ > ld r4,RTASBASE(r4) /* get the rtas->base value */ > > + li r0,0 > + mtmsrd r0,1 /* disable RI before using SRR0/1 */ > + > mtspr SPRN_SRR0,r5 > mtspr SPRN_SRR1,r6 > RFI_TO_KERNEL