From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xz6Xd4mzczDqNm for ; Fri, 22 Sep 2017 18:46:41 +1000 (AEST) Received: by mail-wm0-x242.google.com with SMTP id e64so629975wmi.2 for ; Fri, 22 Sep 2017 01:46:40 -0700 (PDT) Sender: Paolo Bonzini Subject: Re: [PATCH] KVM: PPC: Book3S HV: Check for updated HDSISR on P9 HDSI exception To: Michael Neuling , kvm-ppc@vger.kernel.org, kvm@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Cc: david@gibson.dropbear.id.au, paulus@samba.org, benh@kernel.crashing.org References: <20170915052614.8231-1-mikey@neuling.org> From: Paolo Bonzini Message-ID: Date: Fri, 22 Sep 2017 10:46:36 +0200 MIME-Version: 1.0 In-Reply-To: <20170915052614.8231-1-mikey@neuling.org> Content-Type: text/plain; charset=utf-8 List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On 15/09/2017 07:26, Michael Neuling wrote: > On POWER9 DD2.1 and below, sometimes on a Hypervisor Data Storage > Interrupt (HDSI) the HDSISR is not be updated at all. > > To work around this we put a canary value into the HDSISR before > returning to a guest and then check for this canary when we take a > HDSI. If we find the canary on a HDSI, we know the hardware didn't > update the HDSISR. In this case we return to the guest to retake the > HDSI which should correctly update the HDSISR the second time HDSI > entry. > > After talking to Paulus we've applied this workaround to all POWER9 > CPUs. The workaround of returning to the guest shouldn't ever be > triggered on well behaving CPU. The extra instructions should have > negligible performance impact. > > Signed-off-by: Michael Neuling > --- > arch/powerpc/kvm/book3s_hv_rmhandlers.S | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S > index 663a4a861e..70dca60569 100644 > --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S > +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S > @@ -1118,6 +1118,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) > BEGIN_FTR_SECTION > mtspr SPRN_PPR, r0 > END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) > + > +/* Move canary into DSISR to check for later */ > +BEGIN_FTR_SECTION > + li r0, 0x7fff > + mtspr SPRN_HDSISR, r0 > +END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) > + > ld r0, VCPU_GPR(R0)(r4) > ld r4, VCPU_GPR(R4)(r4) > > @@ -1947,9 +1954,14 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX) > kvmppc_hdsi: > ld r3, VCPU_KVM(r9) > lbz r0, KVM_RADIX(r3) > - cmpwi r0, 0 > mfspr r4, SPRN_HDAR > mfspr r6, SPRN_HDSISR > +BEGIN_FTR_SECTION > + /* Look for DSISR canary. If we find it, retry instruction */ > + cmpdi r6, 0x7fff > + beq 6f > +END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) > + cmpwi r0, 0 > bne .Lradix_hdsi /* on radix, just save DAR/DSISR/ASDR */ > /* HPTE not found fault or protection fault? */ > andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h > Applied to kvm/master, thanks. Paolo