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Wed, 2 Aug 2023 14:18:21 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.9.0-alpha0-624-g7714e4406d-fm-20230801.001-g7714e440 Mime-Version: 1.0 Message-Id: In-Reply-To: References: <20230801-bitwise-v1-1-799bec468dc4@google.com> <20230802161553.GA2108867@dev-arch.thelio-3990X> Date: Wed, 02 Aug 2023 20:17:32 +0200 From: "Arnd Bergmann" To: "Linus Torvalds" , "Nathan Chancellor" , "Michael Ellerman" , "Will Deacon" , "Catalin Marinas" Subject: Re: [PATCH] word-at-a-time: use the same return type for has_zero regardless of endianness Content-Type: text/plain X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Linux-Arch , Tom Rix , llvm@lists.linux.dev, Nick Desaulniers , linux-kernel@vger.kernel.org, linuxppc-dev Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Wed, Aug 2, 2023, at 19:37, Linus Torvalds wrote: > On Wed, 2 Aug 2023 at 09:16, Nathan Chancellor wrote: >> >> We see this warning with ARCH=arm64 defconfig + CONFIG_CPU_BIG_ENDIAN=y. > > Oh Christ. I didn't even realize that arm64 allowed a BE config. > > The config option goes back to 2013 - are there actually BE user space > implementations around? At least NXP's Layerscape and Huawei's SoCs ended up in big-endian appliances, running legacy software ported from mips or powerpc. I agree this was a mistake, but that wasn't nearly as obvious ten years ago when there were still new BE-only sparc, mips and powerpc put on the market -- that really only ended in 2017. > People, why do we do that? That's positively crazy. BE is dead and > should be relegated to legacy platforms. There are no advantages to > being different just for the sake of being different - any "security > by obscurity" argument would be far outweighed by the inconvenience to > actual users. > > Yes, yes, I know the aarch64 architecture technically allows BE > implementations - and apparently you can even do it by exception > level, which I had to look up. But do any actually exist? > > Does the kernel even work right in BE mode? It's really easy to miss > some endianness check when all the actual hardware and use is LE, and > when (for example) instruction encoding and IO is then always LE > anyway. This was always only done for compatibility with non-portable software when companies with large custom network stacks argued that it was cheaper to build the entire open source software to big-endian than port their own product to little-endian. ;-) We (Linaro) used to test all toolchain and kernel releases in big-endian mode as member companies had customers that asked for it, but that stopped a while ago as those legacy software stacks either got more portable or got replaced over time. Many Arm systems won't boot BE kernels any more because UEFI firmware only supports LE, or because of driver bugs. Virtual machines are still likely to work fine though. I'm fairly sure that all Arm Cortex and Neoverse cores still\ support BE mode in all exception levels, OTOH at least Apple's custom CPUs do not implement it at all. Arnd