From: Kumar Gala <kumar.gala@freescale.com>
To: "Chiradeep Vittal" <chiradeep@matissenetworks.com>
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: Linux Kernel Issue: MPC8540 Errata (CPU29)
Date: Wed, 27 Apr 2005 13:36:42 -0500 [thread overview]
Message-ID: <e29792bf3239d4cfb5861e7826300795@freescale.com> (raw)
In-Reply-To: <F237EFC9919B064C8BF5A44CDA5DA0C212F678@matisse01.matissenetworks.com>
On Apr 27, 2005, at 12:46 PM, Chiradeep Vittal wrote:
> We're running Linux Kernel 2.4.26 on an 8540 ADS derivative. We're
> seeing an
> "illegal instruction"=A0 (SIGILL) exception under some circumstances
> (during a pthread_create call). We were wondering if this could be a
> symptom of
> CPU29 and if there is a patch available for CPU29.
>
> "CPU29 L1 instruction cache gets multiple entries for same line after
> change
> in MSR[IS] bit "
>
> www.freescale.com/files/32bit/doc/errata/MPC8540CE.pdf
The way the Linux kernel manages the MMU on e500 it doesn't actually=20
ever modify MSR[IS] or MSR[DS]. They are always zero so I dont believe=20=
you are hitting this errata.
Are you running with math emulation turned on? Do you know what the=20
instruction is that causes the SIGILL?
- kumar
next prev parent reply other threads:[~2005-04-27 18:36 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-04-27 17:46 Linux Kernel Issue: MPC8540 Errata (CPU29) Chiradeep Vittal
2005-04-27 18:36 ` Kumar Gala [this message]
2005-09-27 15:30 ` How to use SPE on MPC8541 Gérard Guével
2005-09-27 15:56 ` Andy Fleming
2005-09-27 17:36 ` Gérard Guével
2005-09-27 18:50 ` Andy Fleming
2005-09-28 8:02 ` Gérard Guével
2005-09-28 15:32 ` Andy Fleming
2005-09-29 13:23 ` Gérard Guével
-- strict thread matches above, loose matches on Subject: below --
2005-04-28 18:31 Linux Kernel Issue: MPC8540 Errata (CPU29) Chiradeep Vittal
2005-04-28 18:50 ` Greg Weeks
2005-04-28 22:21 ` Kylo Ginsberg
2005-04-28 23:18 ` Kumar Gala
2005-04-29 6:02 ` Wolfgang Denk
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