MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006

MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006

[Florian Boelstler]

Hi,

I am currently working on a MPC8548-based development system.
Linux kernel version is 2.6.11 with patches delivered from Freescale 
(BSP MPC8548CDS 02/24/2006).

Kernel configuration contains a warning message for CONFIG_PEX:
"This requires hardware modification to work correctly if your CPU 
version < 2.0 and will break the PCI bus. [...]"

I was wondering whether enabling PCIe makes PCI bus functionality 
unusable at all (including kernel functionality for detecting devices 
behind a transparent PCI-to-PCI bridge).

Our setup connects a transparent PLX8516 PCI-to-PCI bridge to the PCIe 
port of the MPC8548 daughter board. Behind that bridge is another PCIe 
capable device.
MPC8548 is configured to run as PCIe host mode.

When trying to lookup the PCIe devices using lspci I can only see the 
PPC itself and the bridge.
However I cannot see the device(s) behind the bridge.

Is there another method for detecting PCI(e) devices?
Is "BSP MPC8548CDS 02/24/2006" the latest version corresponding to that 
hardware?

Thanks in advance,

   Florian

Re: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006

[Vitaly Bordug]

On Mon, 26 Jun 2006 12:48:27 +0200
Florian Boelstler <euphoria@arcor.de> wrote:

> Hi,
>=20
> I am currently working on a MPC8548-based development system.
> Linux kernel version is 2.6.11 with patches delivered from Freescale=20
> (BSP MPC8548CDS 02/24/2006).
>=20
> Kernel configuration contains a warning message for CONFIG_PEX:
> "This requires hardware modification to work correctly if your CPU=20
> version < 2.0 and will break the PCI bus. [...]"
>=20
> I was wondering whether enabling PCIe makes PCI bus functionality=20
> unusable at all (including kernel functionality for detecting devices=20
> behind a transparent PCI-to-PCI bridge).
>=20
IIRC,yes.

> Our setup connects a transparent PLX8516 PCI-to-PCI bridge to the PCIe=20
> port of the MPC8548 daughter board. Behind that bridge is another PCIe=20
> capable device.
> MPC8548 is configured to run as PCIe host mode.
>=20
> When trying to lookup the PCIe devices using lspci I can only see the=20
> PPC itself and the bridge.
> However I cannot see the device(s) behind the bridge.
>=20

That's highly depends on silicon and Arcadia rev. you are using. There are =
some other details=20
about PCI-XP, but to inquire the certain information, you should contact FS=
L support.
> Is there another method for detecting PCI(e) devices?
> Is "BSP MPC8548CDS 02/24/2006" the latest version corresponding to that=20
> hardware?
>=20
=46rom what I know, yes, 2/24 is the latest. But you'll need some tricks in o=
rder to utilize PCI-xp...


--=20
Sincerely,=20
Vitaly

Re: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006

[Florian Boelstler]

Vitaly Bordug schrieb:
> From what I know, yes, 2/24 is the latest. But you'll need some tricks in order to utilize PCI-xp...

Thanks for your response. I will contact FSL.
May you share those tricks for PCIe utilization? :)

   Florian

RE: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006

[Zhang Wei-r63237]

Hi, 

Please see inline comments.

Best Regards,
Zhang Wei

> -----Original Message-----
> From: 
> linuxppc-embedded-bounces+wei.zhang=freescale.com@ozlabs.org 
> [mailto:linuxppc-embedded-bounces+wei.zhang=freescale.com@ozla
> bs.org] On Behalf Of Florian Boelstler
> Sent: Monday, June 26, 2006 6:48 PM
> To: linuxppc-embedded@ozlabs.org
> Subject: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006
> 
> Hi,
> 
> I am currently working on a MPC8548-based development system.
> Linux kernel version is 2.6.11 with patches delivered from 
> Freescale (BSP MPC8548CDS 02/24/2006).
> 
> Kernel configuration contains a warning message for CONFIG_PEX:
> "This requires hardware modification to work correctly if 
> your CPU version < 2.0 and will break the PCI bus. [...]"
> 
> I was wondering whether enabling PCIe makes PCI bus 
> functionality unusable at all (including kernel functionality 
> for detecting devices behind a transparent PCI-to-PCI bridge).

The interrupts polarity of MPC8548 PCIe controller is reversed to PCI. That's an errata of MPC8548.
So you must rework to fix them. You can find the detail from user manual of bsp.

> 
> Our setup connects a transparent PLX8516 PCI-to-PCI bridge to 
> the PCIe port of the MPC8548 daughter board. Behind that 
> bridge is another PCIe capable device.
> MPC8548 is configured to run as PCIe host mode.
> 
> When trying to lookup the PCIe devices using lspci I can only 
> see the PPC itself and the bridge.
> However I cannot see the device(s) behind the bridge.

Yes, that's also an errata to MPC8548 PCIe controller.
Trying to apply below patch code:

diff -u -r1.1.1.2.2.3 ppc85xx_setup.c
--- arch/ppc/syslib/ppc85xx_setup.c	7 Apr 2006 08:57:50 -0000	1.1.1.2.2.3
+++ arch/ppc/syslib/ppc85xx_setup.c	27 Jun 2006 02:45:54 -0000
@@ -256,6 +256,7 @@
 {
 	volatile struct ccsr_pex *pex;
 	unsigned short temps;
+	unsigned int pribus;
 	bd_t *binfo = (bd_t *) __res;
 
 	pex = ioremap(binfo->bi_immr_base + MPC85xx_PEX_OFFSET,
@@ -265,6 +266,11 @@
 	temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 	early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);
 	early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
+
+	/* PCIE Bus, Fix the MPC8548 host bridge's location to bus 0xFF. */
+	early_read_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, &pribus);
+	pribus = (pribus & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16);
+	early_write_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, pribus);
 
 	/* Disable all windows (except powar0 since its ignored) */
 	pex->pexowar1 = 0; 
> 
> Is there another method for detecting PCI(e) devices?
> Is "BSP MPC8548CDS 02/24/2006" the latest version 
> corresponding to that hardware?

Yes, it's the last version.

> 
> Thanks in advance,
> 
>    Florian
> 
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> 

Re: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006

[Florian Boelstler]

Hi,

thanks for your quick response.
I'll try the proposed changes today.

Zhang Wei-r63237 schrieb:
> Trying to apply below patch code:
 > [...]

Is there a publicly available source for patches to the current BSP?
Are there any other PCIe-related fixes?

Best regards,

   Florian

RE: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006

[Zhang Wei-r63237]

> 
> Is there a publicly available source for patches to the current BSP?
> Are there any other PCIe-related fixes?

It's an add-on PCIe patch. We have tested it on MPC8641, but we have no PCIe-PCI bridge on MPC8548 platform to do more test. So if you verify it, I'll commit it. :)

> 
> Best regards,
> 
>    Florian
> 
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> 

Re: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006

[Florian Boelstler]

Hi,

Zhang Wei-r63237 schrieb:
> It's an add-on PCIe patch. We have tested it on MPC8641, but we have no PCIe-PCI bridge on MPC8548 platform to do more test. So if you verify it, I'll commit it. :)

We did the hardware fix described in the BSP user's manual to make PCIe 
work (according to the manual section 2.1, step 3).
I.e.
  1) removed R193 and R194 on the carrier card (rev 1.2)
  2) removed RN1 on the CPU daughter card
  2a) connected pad3 of RN1 to pin3 of U12 (IRQ0)
  2b) connected pad2 of RN1 to pin4 of U12 (IRQ1)

Does this fix the interrupt polarity problem (as well)?

We applied the provided kernel patch as well.
IMHO that patch just moves the local PCIe root-complex "out-of-space" so 
no detection of that one occurs any more.
This is what actually happens when "lspci" is run.

However we still don't see any devices behind the PCIe switch (e.g. a 
transparent PLX8516). It seems that the enumeration process (traversing 
through the bus hierarchy) in the kernel is somehow disabled.
Bottom line: Only one device accessible at all on the PCIe port.

Any further ideas?

Thanks,

   Florian

RE: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006

[Zhang Wei-r63237]

> We did the hardware fix described in the BSP user's manual to 
> make PCIe work (according to the manual section 2.1, step 3).
> I.e.
>   1) removed R193 and R194 on the carrier card (rev 1.2)
>   2) removed RN1 on the CPU daughter card
>   2a) connected pad3 of RN1 to pin3 of U12 (IRQ0)
>   2b) connected pad2 of RN1 to pin4 of U12 (IRQ1)
> 
> Does this fix the interrupt polarity problem (as well)?

Yes, I think so. You can plug a PCIe ethernet card to test it. 

> 
> We applied the provided kernel patch as well.
> IMHO that patch just moves the local PCIe root-complex 
> "out-of-space" so no detection of that one occurs any more.
> This is what actually happens when "lspci" is run.
> 
> However we still don't see any devices behind the PCIe switch 
> (e.g. a transparent PLX8516). It seems that the enumeration 
> process (traversing through the bus hierarchy) in the kernel 
> is somehow disabled.

:-), Maybe it's need more study. Could you enable the DEBUG and post the kernel verbose message?

> Bottom line: Only one device accessible at all on the PCIe port.
> 
> Any further ideas?
> 
> Thanks,
> 
>    Florian
> 
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> 

Re: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006

[Florian Boelstler]

Hi,

Zhang Wei-r63237 schrieb:
> Yes, I think so. You can plug a PCIe ethernet card to test it. 

A single device always works.

> :-), Maybe it's need more study. Could you enable the DEBUG and post the kernel verbose message?

We added lots of debug output and made some modifications (mostly delays 
between calls to early_read_config_dword() and 
early_write_config_dword() in pci_auto.c) and came to the conclusion 
that generic bridge devices (PCIe-to-PCI), even in a cascaded setup of 
three bridges, work fine.

However a PCIe switch (PLX8516/8532) doesn't work. The MPC8548 only 
detects a single device (i.e. primary side of the switch).
We are going to analyze the problem more deeply soon. It seems that the 
configuration space of that devices isn't properly set up.

The provided patch doesn't make any difference, besides that it is moved 
to a location where the PPC itself is not detected.

Please keep us informed if there is any progress besides Freescale, as I 
will do.

Cheers,

   Florian

RE: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006

[Zhang Wei-r63237]

Hi, 

> -----Original Message-----
> From: 
> linuxppc-embedded-bounces+wei.zhang=freescale.com@ozlabs.org 
> [mailto:linuxppc-embedded-bounces+wei.zhang=freescale.com@ozla
> bs.org] On Behalf Of Florian Boelstler
> Sent: Monday, July 03, 2006 2:38 PM
> To: linuxppc-embedded@ozlabs.org
> Subject: Re: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006
> 
> Hi,
> 
> Zhang Wei-r63237 schrieb:
> > Yes, I think so. You can plug a PCIe ethernet card to test it. 
> 
> A single device always works.
> 
> > :-), Maybe it's need more study. Could you enable the DEBUG 
> and post the kernel verbose message?
> 
> We added lots of debug output and made some modifications 
> (mostly delays between calls to early_read_config_dword() and
> early_write_config_dword() in pci_auto.c) and came to the 
> conclusion that generic bridge devices (PCIe-to-PCI), even in 
> a cascaded setup of three bridges, work fine.

Yea, that's a good news.

> 
> However a PCIe switch (PLX8516/8532) doesn't work. The 
> MPC8548 only detects a single device (i.e. primary side of 
> the switch).
> We are going to analyze the problem more deeply soon. It 
> seems that the configuration space of that devices isn't 
> properly set up.

Just a suggestion.
Do you see below codes in mpc85xx_pex_errata.c(in read and write functions)?
	if (devfn != 0x0) 
		return PCIBIOS_DEVICE_NOT_FOUND;
Change them to:
	if (devfn != 0x0 && bus->number ==0) 
		return PCIBIOS_DEVICE_NOT_FOUND;
And try again. :-)
(If you apply my patch, please use "if (devfn != 0x0 && bus->number ==0xff)" )

> 
> The provided patch doesn't make any difference, besides that 
> it is moved to a location where the PPC itself is not detected.
> 
This patch fix an issue of MPC8641 PCI-Ex controller. It seems MPC8548 has no that issue. Well then fotget it.

Thanks!
Zhang Wei

> Please keep us informed if there is any progress besides 
> Freescale, as I will do.
> 
> Cheers,
> 
>    Florian
> 
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> 

RE: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006

[Ho Jeffrey-r26191]

Hi Florian,

I have done the PCI config cycle under u-boot. This is very simple and able to find the PEX EP attached to the MPC8548.
In this log, it is reading a pair of MPC8548E connected together using PEX.
Please see the log below:

U-Boot 1.1.4 (Apr 12 2006 - 11:40:53)

CPU:   8548_E, Version: 1.1, (0x80390011)
Core:  e500v2, Version: 1.0, (0x80210010)
Clock Configuration:
       CPU:1333 MHz, CCB: 533 MHz,
       DDR: 266 MHz, LBC:  33 MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled

Board: MPC85xx Processor Card Rev. A.
       -- Boot Flash is U30

SRIO:  X4 2.5Gbps
PEX :  X4 2.5Gbps
PCI1:  32 bit, async
PCI2:  disabled
I2C:   ready
DRAM:  Initializing
DDR:   256 MB
FLASH: 16 MB
L2 cache 512KB: enabled
In:    serial
Out:   serial
Err:   serial
Net:   eTSEC0: PHY is Marvell 88E1111S (1410cc1)
eTSEC1: PHY is Realtek RTL821x (1cc912)
eTSEC2: PHY is Marvell 88E1111S (1410cc1)
eTSEC3: PHY id ffffffff is not supported!
eTSEC0, eTSEC1, eTSEC2 [PRIME], eTSEC3
eTSEC0 & eTSEC1 in Reduce mode
eTSEC2 & eTSEC3 in Reduce mode
Hit any key to stop autoboot:  0
MPC8548E_Rev1.1=> mm e000a000      	<-setup command register
e000a000: 8000f800 ? 80000004		   Bus master, SERR, Memory space
e000a004: 02001000 ? 06011000
e000a008: 00000000 ? .
MPC8548E_Rev1.1=> mm e000a000	<-Set secondary bus num = 1	
e000a000: 80000004 ? 80000018		  Subordinate bus num = 3
e000a004: 00000000 ? 00010300
e000a008: 00000000 ? .
MPC8548E_Rev1.1=> mm e000a000	<-Check PEX agent ID
e000a000: 80000018 ? 80010000
e000a004: 57191200 ? .
MPC8548E_Rev1.1=> mm e000a000	<-Set PEX agent BAR0 (PEXCSRBAR) 
e000a000: 80010010 ? 80010010		  PEXCSRBAR = 0x80000000
e000a004: 00000000 ? 00000080		  This is the PCI address space
e000a008: 00000000 ? .
MPC8548E_Rev1.1=> mm e000a000	<-Set PEX agent command register
e000a000: 80010014 ? 80010004		   Bus master, SERR, Memory space
e000a004: 00001000 ? 06011000
e000a008: 00000000 ? .
MPC8548E_Rev1.1=> 
mw e000ac20 00080000;		<-Set TAR = 0x80000000 (PCI address space)
mw e000ac24 0;				<-Set 32:64bit TAR = 0x0 (PCI address space)
mw e000ac28 000a0000;		<-Set WBA = 0xa0000000 (ECM, e500 address space) 
mw e000ac30 8004401A			<-Set normal R/W, enable Outbound window
MPC8548E_Rev1.1=>
MPC8548E_Rev1.1=>
MPC8548E_Rev1.1=> mm e000a000	<-check PEX agent BAR0 if written
e000a000: 80010010 ?
e000a004: 00000080 ? .
MPC8548E_Rev1.1=> md a0000000	<-read PEX agent CCSRBAR address use 0xa0000000
a0000000: 000ff700 00000000 00000000 00000000    ................
a0000010: 00000000 00000000 00000000 00000000    ................
a0000020: 00000000 00000000 00000000 00000000    ................
a0000030: 00000000 00000000 00000000 00000000    ................
a0000040: 00000000 00000000 00000000 00000000    ................
a0000050: 00000000 00000000 00000000 00000000    ................
a0000060: 00000000 00000000 00000000 00000000    ................
a0000070: 00000000 00000000 00000000 00000000    ................
a0000080: 00000000 00000000 00000000 00000000    ................
a0000090: 00000000 00000000 00000000 00000000    ................
a00000a0: 00000000 00000000 00000000 00000000    ................
a00000b0: 00000000 00000000 00000000 00000000    ................
a00000c0: 00000000 00000000 00000000 00000000    ................
a00000d0: 00000000 00000000 00000000 00000000    ................
a00000e0: 00000000 00000000 00000000 00000000    ................
a00000f0: 00000000 00000000 00000000 00000000    ................ 

Regards,
Jeffrey Ho
Freescale Semiconductor HK Ltd
Tel: 852-26668050
 

> -----Original Message-----
> From: 
> linuxppc-embedded-bounces+r26191=freescale.com@ozlabs.org 
> [mailto:linuxppc-embedded-bounces+r26191=freescale.com@ozlabs.
> org] On Behalf Of Florian Boelstler
> Sent: Monday, June 26, 2006 6:48 PM
> To: linuxppc-embedded@ozlabs.org
> Subject: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006
> 
> Hi,
> 
> I am currently working on a MPC8548-based development system.
> Linux kernel version is 2.6.11 with patches delivered from 
> Freescale (BSP MPC8548CDS 02/24/2006).
> 
> Kernel configuration contains a warning message for CONFIG_PEX:
> "This requires hardware modification to work correctly if 
> your CPU version < 2.0 and will break the PCI bus. [...]"
> 
> I was wondering whether enabling PCIe makes PCI bus 
> functionality unusable at all (including kernel functionality 
> for detecting devices behind a transparent PCI-to-PCI bridge).
> 
> Our setup connects a transparent PLX8516 PCI-to-PCI bridge to 
> the PCIe port of the MPC8548 daughter board. Behind that 
> bridge is another PCIe capable device.
> MPC8548 is configured to run as PCIe host mode.
> 
> When trying to lookup the PCIe devices using lspci I can only 
> see the PPC itself and the bridge.
> However I cannot see the device(s) behind the bridge.
> 
> Is there another method for detecting PCI(e) devices?
> Is "BSP MPC8548CDS 02/24/2006" the latest version 
> corresponding to that hardware?
> 
> Thanks in advance,
> 
>    Florian
> 
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> 

Re: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006

[Florian Boelstler]

Hi Jeffrey,

 > I have done the PCI config cycle under u-boot. This is very simple 
and > able to find the PEX EP attached to the MPC8548.
 > In this log, it is reading a pair of MPC8548E connected together 
using > PEX.
 > Please see the log below:
[ ... ]

thanks for sharing this piece of information.
I will investigate if this matches the way it is done in the kernel.

Thanks,

   Florian

Ho Jeffrey-r26191 schrieb:
> Hi Florian,
> 
> 
> U-Boot 1.1.4 (Apr 12 2006 - 11:40:53)
> 
> CPU:   8548_E, Version: 1.1, (0x80390011)
> Core:  e500v2, Version: 1.0, (0x80210010)
> Clock Configuration:
>        CPU:1333 MHz, CCB: 533 MHz,
>        DDR: 266 MHz, LBC:  33 MHz
> L1:    D-cache 32 kB enabled
>        I-cache 32 kB enabled
> 
> Board: MPC85xx Processor Card Rev. A.
>        -- Boot Flash is U30
> 
> SRIO:  X4 2.5Gbps
> PEX :  X4 2.5Gbps
> PCI1:  32 bit, async
> PCI2:  disabled
> I2C:   ready
> DRAM:  Initializing
> DDR:   256 MB
> FLASH: 16 MB
> L2 cache 512KB: enabled
> In:    serial
> Out:   serial
> Err:   serial
> Net:   eTSEC0: PHY is Marvell 88E1111S (1410cc1)
> eTSEC1: PHY is Realtek RTL821x (1cc912)
> eTSEC2: PHY is Marvell 88E1111S (1410cc1)
> eTSEC3: PHY id ffffffff is not supported!
> eTSEC0, eTSEC1, eTSEC2 [PRIME], eTSEC3
> eTSEC0 & eTSEC1 in Reduce mode
> eTSEC2 & eTSEC3 in Reduce mode
> Hit any key to stop autoboot:  0
> MPC8548E_Rev1.1=> mm e000a000      	<-setup command register
> e000a000: 8000f800 ? 80000004		   Bus master, SERR, Memory space
> e000a004: 02001000 ? 06011000
> e000a008: 00000000 ? .
> MPC8548E_Rev1.1=> mm e000a000	<-Set secondary bus num = 1	
> e000a000: 80000004 ? 80000018		  Subordinate bus num = 3
> e000a004: 00000000 ? 00010300
> e000a008: 00000000 ? .
> MPC8548E_Rev1.1=> mm e000a000	<-Check PEX agent ID
> e000a000: 80000018 ? 80010000
> e000a004: 57191200 ? .
> MPC8548E_Rev1.1=> mm e000a000	<-Set PEX agent BAR0 (PEXCSRBAR) 
> e000a000: 80010010 ? 80010010		  PEXCSRBAR = 0x80000000
> e000a004: 00000000 ? 00000080		  This is the PCI address space
> e000a008: 00000000 ? .
> MPC8548E_Rev1.1=> mm e000a000	<-Set PEX agent command register
> e000a000: 80010014 ? 80010004		   Bus master, SERR, Memory space
> e000a004: 00001000 ? 06011000
> e000a008: 00000000 ? .
> MPC8548E_Rev1.1=> 
> mw e000ac20 00080000;		<-Set TAR = 0x80000000 (PCI address space)
> mw e000ac24 0;				<-Set 32:64bit TAR = 0x0 (PCI address space)
> mw e000ac28 000a0000;		<-Set WBA = 0xa0000000 (ECM, e500 address space) 
> mw e000ac30 8004401A			<-Set normal R/W, enable Outbound window
> MPC8548E_Rev1.1=>
> MPC8548E_Rev1.1=>
> MPC8548E_Rev1.1=> mm e000a000	<-check PEX agent BAR0 if written
> e000a000: 80010010 ?
> e000a004: 00000080 ? .
> MPC8548E_Rev1.1=> md a0000000	<-read PEX agent CCSRBAR address use 0xa0000000
> a0000000: 000ff700 00000000 00000000 00000000    ................
> a0000010: 00000000 00000000 00000000 00000000    ................
> a0000020: 00000000 00000000 00000000 00000000    ................
> a0000030: 00000000 00000000 00000000 00000000    ................
> a0000040: 00000000 00000000 00000000 00000000    ................
> a0000050: 00000000 00000000 00000000 00000000    ................
> a0000060: 00000000 00000000 00000000 00000000    ................
> a0000070: 00000000 00000000 00000000 00000000    ................
> a0000080: 00000000 00000000 00000000 00000000    ................
> a0000090: 00000000 00000000 00000000 00000000    ................
> a00000a0: 00000000 00000000 00000000 00000000    ................
> a00000b0: 00000000 00000000 00000000 00000000    ................
> a00000c0: 00000000 00000000 00000000 00000000    ................
> a00000d0: 00000000 00000000 00000000 00000000    ................
> a00000e0: 00000000 00000000 00000000 00000000    ................
> a00000f0: 00000000 00000000 00000000 00000000    ................ 
> 
> Regards,
> Jeffrey Ho
> Freescale Semiconductor HK Ltd
> Tel: 852-26668050
>  
> 
>> -----Original Message-----
>> From: 
>> linuxppc-embedded-bounces+r26191=freescale.com@ozlabs.org 
>> [mailto:linuxppc-embedded-bounces+r26191=freescale.com@ozlabs.
>> org] On Behalf Of Florian Boelstler
>> Sent: Monday, June 26, 2006 6:48 PM
>> To: linuxppc-embedded@ozlabs.org
>> Subject: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006
>>
>> Hi,
>>
>> I am currently working on a MPC8548-based development system.
>> Linux kernel version is 2.6.11 with patches delivered from 
>> Freescale (BSP MPC8548CDS 02/24/2006).
>>
>> Kernel configuration contains a warning message for CONFIG_PEX:
>> "This requires hardware modification to work correctly if 
>> your CPU version < 2.0 and will break the PCI bus. [...]"
>>
>> I was wondering whether enabling PCIe makes PCI bus 
>> functionality unusable at all (including kernel functionality 
>> for detecting devices behind a transparent PCI-to-PCI bridge).
>>
>> Our setup connects a transparent PLX8516 PCI-to-PCI bridge to 
>> the PCIe port of the MPC8548 daughter board. Behind that 
>> bridge is another PCIe capable device.
>> MPC8548 is configured to run as PCIe host mode.
>>
>> When trying to lookup the PCIe devices using lspci I can only 
>> see the PPC itself and the bridge.
>> However I cannot see the device(s) behind the bridge.
>>
>> Is there another method for detecting PCI(e) devices?
>> Is "BSP MPC8548CDS 02/24/2006" the latest version 
>> corresponding to that hardware?
>>
>> Thanks in advance,
>>
>>    Florian
>>
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>>

Re: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006

[Florian Boelstler]

Hi Jeffrey,

I got one more question.
Is it enough to jumper the MPC8548 to an endpoint device?
Or is some additional code required (like your U-Boot commands) to make 
a MPC8548 work as an EP.
Up to now I was assuming there is a certain EEPROM that contains a 
sufficient PCIe EP configuration.

Thanks,

   Florian