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From: Segher Boessenkool <segher@kernel.crashing.org>
Subject: Re: TSI ethernet PHY question
Date: Fri, 25 May 2007 16:17:32 +0200
To: David Gibson <david@gibson.dropbear.id.au>
Cc: Alexandre Bounine <Alexandre.Bounine@tundra.com>,
	linuxppc-dev list <linuxppc-dev@ozlabs.org>
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>> Since the specific bug we're talking about here is not a
>> problem with the PHY, but a miswiring on the board, I wouldn't
>> put a flag for the workaround in the phy node in the device
>> tree.  It certainly is an option though.
>
> Uh.. something to bear in mind is that although it is a board
> miswiring, it's of a type that it will plausibly occur in other
> boards.

It is possible yes.

> IIRC, if a LED is attached to this PHY the workaround is
> necessary, or something similar.

Only if it is attached the wrong way, so it acts as a
pull-up (or was it pull-down) during chip reset.

>   So there is value in having a
> particular flag for this rather than just looking at the board model.

A bit, maybe.


Segher