From: Christophe Leroy <christophe.leroy@csgroup.eu>
To: Herve Codina <herve.codina@bootlin.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Andrew Lunn <andrew@lunn.ch>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>, Lee Jones <lee@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Qiang Zhao <qiang.zhao@nxp.com>, Li Yang <leoyang.li@nxp.com>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>, Jaroslav Kysela <perex@perex.cz>,
Takashi Iwai <tiwai@suse.com>,
Shengjiu Wang <shengjiu.wang@gmail.com>,
Xiubo Li <Xiubo.Lee@gmail.com>,
Fabio Estevam <festevam@gmail.com>,
Nicolin Chen <nicoleotsuka@gmail.com>,
Randy Dunlap <rdunlap@infradead.org>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v2 16/28] soc: fsl: cpm1: qmc: Handle timeslot entries at channel start() and stop()
Date: Tue, 8 Aug 2023 08:09:50 +0000 [thread overview]
Message-ID: <f2a94aa0-84e3-a314-f232-1a1a47590c03@csgroup.eu> (raw)
In-Reply-To: <20230726150225.483464-17-herve.codina@bootlin.com>
Le 26/07/2023 à 17:02, Herve Codina a écrit :
> In order to support runtime timeslot route changes, enable the
> channel timeslot entries at channel start() and disable them at
> channel stop().
>
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> drivers/soc/fsl/qe/qmc.c | 175 ++++++++++++++++++++++++++++++++++++---
> 1 file changed, 163 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
> index dc113463fbc7..258a34641551 100644
> --- a/drivers/soc/fsl/qe/qmc.c
> +++ b/drivers/soc/fsl/qe/qmc.c
> @@ -177,6 +177,7 @@ struct qmc_chan {
> struct qmc *qmc;
> void __iomem *s_param;
> enum qmc_mode mode;
> + spinlock_t ts_lock; /* Protect timeslots */
> u64 tx_ts_mask_avail;
> u64 tx_ts_mask;
> u64 rx_ts_mask_avail;
> @@ -265,6 +266,7 @@ static inline void qmc_setbits32(void __iomem *addr, u32 set)
> int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info)
> {
> struct tsa_serial_info tsa_info;
> + unsigned long flags;
> int ret;
>
> /* Retrieve info from the TSA related serial */
> @@ -272,6 +274,8 @@ int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info)
> if (ret)
> return ret;
>
> + spin_lock_irqsave(&chan->ts_lock, flags);
> +
> info->mode = chan->mode;
> info->rx_fs_rate = tsa_info.rx_fs_rate;
> info->rx_bit_rate = tsa_info.rx_bit_rate;
> @@ -280,6 +284,8 @@ int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info)
> info->tx_bit_rate = tsa_info.tx_bit_rate;
> info->nb_rx_ts = hweight64(chan->rx_ts_mask);
>
> + spin_unlock_irqrestore(&chan->ts_lock, flags);
> +
> return 0;
> }
> EXPORT_SYMBOL(qmc_chan_get_info);
> @@ -683,6 +689,40 @@ static int qmc_chan_setup_tsa_32tx(struct qmc_chan *chan, const struct tsa_seria
> return 0;
> }
>
> +static int qmc_chan_setup_tsa_tx(struct qmc_chan *chan, bool enable)
> +{
> + struct tsa_serial_info info;
> + int ret;
> +
> + /* Retrieve info from the TSA related serial */
> + ret = tsa_serial_get_info(chan->qmc->tsa_serial, &info);
> + if (ret)
> + return ret;
> +
> + /* Setup entries */
> + if (chan->qmc->is_tsa_64rxtx)
> + return qmc_chan_setup_tsa_64rxtx(chan, &info, enable);
> +
> + return qmc_chan_setup_tsa_32tx(chan, &info, enable);
> +}
> +
> +static int qmc_chan_setup_tsa_rx(struct qmc_chan *chan, bool enable)
> +{
> + struct tsa_serial_info info;
> + int ret;
> +
> + /* Retrieve info from the TSA related serial */
> + ret = tsa_serial_get_info(chan->qmc->tsa_serial, &info);
> + if (ret)
> + return ret;
> +
> + /* Setup entries */
> + if (chan->qmc->is_tsa_64rxtx)
> + return qmc_chan_setup_tsa_64rxtx(chan, &info, enable);
> +
> + return qmc_chan_setup_tsa_32rx(chan, &info, enable);
> +}
> +
> static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool enable)
> {
> struct tsa_serial_info info;
> @@ -719,6 +759,12 @@ static int qmc_chan_stop_rx(struct qmc_chan *chan)
>
> spin_lock_irqsave(&chan->rx_lock, flags);
>
> + if (chan->is_rx_stopped) {
> + /* The channel is already stopped -> simply return ok */
> + ret = 0;
> + goto end;
> + }
> +
> /* Send STOP RECEIVE command */
> ret = qmc_chan_command(chan, 0x0);
> if (ret) {
> @@ -729,6 +775,15 @@ static int qmc_chan_stop_rx(struct qmc_chan *chan)
>
> chan->is_rx_stopped = true;
>
> + if (!chan->qmc->is_tsa_64rxtx || chan->is_tx_stopped) {
> + ret = qmc_chan_setup_tsa_rx(chan, false);
> + if (ret) {
> + dev_err(chan->qmc->dev, "chan %u: Disable tsa entries failed (%d)\n",
> + chan->id, ret);
> + goto end;
> + }
> + }
> +
> end:
> spin_unlock_irqrestore(&chan->rx_lock, flags);
> return ret;
> @@ -741,6 +796,12 @@ static int qmc_chan_stop_tx(struct qmc_chan *chan)
>
> spin_lock_irqsave(&chan->tx_lock, flags);
>
> + if (chan->is_tx_stopped) {
> + /* The channel is already stopped -> simply return ok */
> + ret = 0;
> + goto end;
> + }
> +
> /* Send STOP TRANSMIT command */
> ret = qmc_chan_command(chan, 0x1);
> if (ret) {
> @@ -751,37 +812,82 @@ static int qmc_chan_stop_tx(struct qmc_chan *chan)
>
> chan->is_tx_stopped = true;
>
> + if (!chan->qmc->is_tsa_64rxtx || chan->is_rx_stopped) {
> + ret = qmc_chan_setup_tsa_tx(chan, false);
> + if (ret) {
> + dev_err(chan->qmc->dev, "chan %u: Disable tsa entries failed (%d)\n",
> + chan->id, ret);
> + goto end;
> + }
> + }
> +
> end:
> spin_unlock_irqrestore(&chan->tx_lock, flags);
> return ret;
> }
>
> +static int qmc_chan_start_rx(struct qmc_chan *chan);
> +
> int qmc_chan_stop(struct qmc_chan *chan, int direction)
> {
> - int ret;
> + bool is_rx_rollback_needed = false;
> + unsigned long flags;
> + int ret = 0;
> +
> + spin_lock_irqsave(&chan->ts_lock, flags);
>
> if (direction & QMC_CHAN_READ) {
> + is_rx_rollback_needed = !chan->is_rx_stopped;
> ret = qmc_chan_stop_rx(chan);
> if (ret)
> - return ret;
> + goto end;
> }
>
> if (direction & QMC_CHAN_WRITE) {
> ret = qmc_chan_stop_tx(chan);
> - if (ret)
> - return ret;
> + if (ret) {
> + /* Restart rx if needed */
> + if (is_rx_rollback_needed)
> + qmc_chan_start_rx(chan);
> + goto end;
> + }
> }
>
> - return 0;
> +end:
> + spin_unlock_irqrestore(&chan->ts_lock, flags);
> + return ret;
> }
> EXPORT_SYMBOL(qmc_chan_stop);
>
> -static void qmc_chan_start_rx(struct qmc_chan *chan)
> +static int qmc_setup_chan_trnsync(struct qmc *qmc, struct qmc_chan *chan);
> +
> +static int qmc_chan_start_rx(struct qmc_chan *chan)
> {
> unsigned long flags;
> + int ret;
>
> spin_lock_irqsave(&chan->rx_lock, flags);
>
> + if (!chan->is_rx_stopped) {
> + /* The channel is already started -> simply return ok */
> + ret = 0;
> + goto end;
> + }
> +
> + ret = qmc_chan_setup_tsa_rx(chan, true);
> + if (ret) {
> + dev_err(chan->qmc->dev, "chan %u: Enable tsa entries failed (%d)\n",
> + chan->id, ret);
> + goto end;
> + }
> +
> + ret = qmc_setup_chan_trnsync(chan->qmc, chan);
> + if (ret) {
> + dev_err(chan->qmc->dev, "chan %u: setup TRNSYNC failed (%d)\n",
> + chan->id, ret);
> + goto end;
> + }
> +
> /* Restart the receiver */
> if (chan->mode == QMC_TRANSPARENT)
> qmc_write32(chan->s_param + QMC_SPE_ZDSTATE, 0x18000080);
> @@ -792,15 +898,38 @@ static void qmc_chan_start_rx(struct qmc_chan *chan)
>
> chan->is_rx_stopped = false;
>
> +end:
> spin_unlock_irqrestore(&chan->rx_lock, flags);
> + return ret;
> }
>
> -static void qmc_chan_start_tx(struct qmc_chan *chan)
> +static int qmc_chan_start_tx(struct qmc_chan *chan)
> {
> unsigned long flags;
> + int ret;
>
> spin_lock_irqsave(&chan->tx_lock, flags);
>
> + if (!chan->is_tx_stopped) {
> + /* The channel is already started -> simply return ok */
> + ret = 0;
> + goto end;
> + }
> +
> + ret = qmc_chan_setup_tsa_tx(chan, true);
> + if (ret) {
> + dev_err(chan->qmc->dev, "chan %u: Enable tsa entries failed (%d)\n",
> + chan->id, ret);
> + goto end;
> + }
> +
> + ret = qmc_setup_chan_trnsync(chan->qmc, chan);
> + if (ret) {
> + dev_err(chan->qmc->dev, "chan %u: setup TRNSYNC failed (%d)\n",
> + chan->id, ret);
> + goto end;
> + }
> +
> /*
> * Enable channel transmitter as it could be disabled if
> * qmc_chan_reset() was called.
> @@ -812,18 +941,39 @@ static void qmc_chan_start_tx(struct qmc_chan *chan)
>
> chan->is_tx_stopped = false;
>
> +end:
> spin_unlock_irqrestore(&chan->tx_lock, flags);
> + return ret;
> }
>
> int qmc_chan_start(struct qmc_chan *chan, int direction)
> {
> - if (direction & QMC_CHAN_READ)
> - qmc_chan_start_rx(chan);
> + bool is_rx_rollback_needed = false;
> + unsigned long flags;
> + int ret = 0;
>
> - if (direction & QMC_CHAN_WRITE)
> - qmc_chan_start_tx(chan);
> + spin_lock_irqsave(&chan->ts_lock, flags);
>
> - return 0;
> + if (direction & QMC_CHAN_READ) {
> + is_rx_rollback_needed = chan->is_rx_stopped;
> + ret = qmc_chan_start_rx(chan);
> + if (ret)
> + goto end;
> + }
> +
> + if (direction & QMC_CHAN_WRITE) {
> + ret = qmc_chan_start_tx(chan);
> + if (ret) {
> + /* Restop rx if needed */
> + if (is_rx_rollback_needed)
> + qmc_chan_stop_rx(chan);
> + goto end;
> + }
> + }
> +
> +end:
> + spin_unlock_irqrestore(&chan->ts_lock, flags);
> + return ret;
> }
> EXPORT_SYMBOL(qmc_chan_start);
>
> @@ -992,6 +1142,7 @@ static int qmc_of_parse_chans(struct qmc *qmc, struct device_node *np)
> }
>
> chan->id = chan_id;
> + spin_lock_init(&chan->ts_lock);
> spin_lock_init(&chan->rx_lock);
> spin_lock_init(&chan->tx_lock);
>
next prev parent reply other threads:[~2023-08-08 8:13 UTC|newest]
Thread overview: 91+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-26 15:01 [PATCH v2 00/28] Add support for QMC HDLC, framer infrastruture and PEF2256 framer Herve Codina
2023-07-26 15:01 ` [PATCH v2 01/28] soc: fsl: cpm1: tsa: Fix __iomem addresses declaration Herve Codina
2023-08-08 7:40 ` Christophe Leroy
2023-07-26 15:01 ` [PATCH v2 02/28] soc: fsl: cpm1: qmc: " Herve Codina
2023-08-08 7:40 ` Christophe Leroy
2023-07-26 15:01 ` [PATCH v2 03/28] soc: fsl: cpm1: qmc: Fix rx channel reset Herve Codina
2023-08-08 7:41 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 04/28] soc: fsl: cpm1: qmc: Extend the API to provide Rx status Herve Codina
2023-08-08 7:41 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 05/28] dt-bindings: net: Add support for QMC HDLC Herve Codina
2023-07-27 8:19 ` Conor Dooley
2023-07-27 9:09 ` Herve Codina
2023-07-27 9:53 ` Conor Dooley
2023-07-27 10:34 ` Herve Codina
2023-07-26 15:02 ` [PATCH v2 06/28] net: wan: " Herve Codina
2023-08-01 9:31 ` Andrew Lunn
2023-08-01 10:07 ` Herve Codina
2023-08-08 8:02 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 07/28] MAINTAINERS: Add the Freescale QMC HDLC driver entry Herve Codina
2023-07-26 15:02 ` [PATCH v2 08/28] soc: fsl: cpm1: qmc: Introduce available timeslots masks Herve Codina
2023-08-01 9:33 ` Andrew Lunn
2023-08-01 10:05 ` Herve Codina
2023-08-08 8:04 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 09/28] soc: fsl: cpm1: qmc: Rename qmc_setup_tsa* to qmc_init_tsa* Herve Codina
2023-08-08 8:04 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 10/28] soc: fsl: cpm1: qmc: Introduce qmc_chan_setup_tsa* Herve Codina
2023-08-01 9:36 ` Andrew Lunn
2023-08-01 10:23 ` Herve Codina
2023-08-08 8:05 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 11/28] soc: fsl: cpm1: qmc: Remove no more needed checks from qmc_check_chans() Herve Codina
2023-08-08 8:05 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 12/28] soc: fsl: cpm1: qmc: Check available timeslots in qmc_check_chans() Herve Codina
2023-08-08 8:06 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 13/28] soc: fsl: cpm1: qmc: Add support for disabling channel TSA entries Herve Codina
2023-08-08 8:06 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 14/28] soc: fsl: cpm1: qmc: Split Tx and Rx TSA entries setup Herve Codina
2023-08-08 8:08 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 15/28] soc: fsl: cpm1: qmc: Introduce is_tsa_64rxtx flag Herve Codina
2023-08-08 8:09 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 16/28] soc: fsl: cpm1: qmc: Handle timeslot entries at channel start() and stop() Herve Codina
2023-08-08 8:09 ` Christophe Leroy [this message]
2023-07-26 15:02 ` [PATCH v2 17/28] soc: fsl: cpm1: qmc: Remove timeslots handling from setup_chan() Herve Codina
2023-08-08 8:10 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 18/28] soc: fsl: cpm1: qmc: Introduce functions to change timeslots at runtime Herve Codina
2023-08-08 8:10 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 19/28] wan: qmc_hdlc: Add runtime timeslots changes support Herve Codina
2023-08-08 8:11 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 20/28] net: wan: Add framer framework support Herve Codina
2023-08-01 9:56 ` Andrew Lunn
2023-08-01 10:32 ` Herve Codina
2023-08-08 8:11 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 21/28] dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer Herve Codina
2023-08-01 10:05 ` Andrew Lunn
2023-08-01 10:35 ` Herve Codina
2023-08-03 0:40 ` Rob Herring
2023-08-03 8:11 ` Herve Codina
2023-07-26 15:02 ` [PATCH v2 22/28] mfd: core: Ensure disabled devices are skiped without aborting Herve Codina
2023-07-27 9:22 ` Lee Jones
2023-07-27 10:18 ` Herve Codina
2023-08-08 8:13 ` Christophe Leroy
2023-08-08 8:44 ` Herve Codina
2023-07-26 15:02 ` [PATCH v2 23/28] net: wan: framer: Add support for the Lantiq PEF2256 framer Herve Codina
2023-08-01 10:22 ` Andrew Lunn
2023-08-01 10:44 ` Herve Codina
2023-08-01 10:52 ` Andrew Lunn
2023-08-01 11:12 ` Herve Codina
2023-08-08 8:15 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 24/28] pinctrl: Add support for the Lantic PEF2256 pinmux Herve Codina
2023-08-07 13:05 ` Linus Walleij
2023-08-07 13:06 ` Linus Walleij
2023-08-07 13:17 ` Andrew Lunn
2023-08-07 14:36 ` Herve Codina
2023-08-07 13:09 ` Mark Brown
2023-08-08 9:00 ` Linus Walleij
2023-08-07 14:27 ` Herve Codina
2023-08-08 8:16 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 25/28] MAINTAINERS: Add the Lantiq PEF2256 driver entry Herve Codina
2023-08-08 8:17 ` Christophe Leroy
2023-07-26 15:02 ` [PATCH v2 26/28] ASoC: codecs: Add support for the framer codec Herve Codina
2023-08-01 10:30 ` Andrew Lunn
2023-08-01 10:45 ` Herve Codina
2023-08-08 8:26 ` Christophe Leroy
2023-08-08 9:06 ` Herve Codina
2023-07-26 15:02 ` [PATCH v2 27/28] dt-bindings: net: fsl,qmc-hdlc: Add framer support Herve Codina
2023-07-27 8:12 ` Conor Dooley
2023-07-27 9:19 ` Herve Codina
2023-08-03 0:42 ` Rob Herring
2023-08-03 8:23 ` Herve Codina
2023-07-26 15:02 ` [PATCH v2 28/28] net: wan: fsl_qmc_hdlc: " Herve Codina
2023-08-08 8:29 ` Christophe Leroy
2023-08-01 10:34 ` [PATCH v2 00/28] Add support for QMC HDLC, framer infrastruture and PEF2256 framer Andrew Lunn
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