Enabling 8xx debug mode

Enabling 8xx debug mode

[Marcelo Tosatti]

Hi Dan,

I know now that the BDI automatically enables debug mode by asserting
the DSCK signal (available through the JTAG port). Is there any way 
to enable debugging mode purely via software?

44.3.1.2 Entering Debug Mode

By appropriately programming the development port during reset, debug
mode can be entered immediately out of reset, thus allowing the user to
debug a ROM-less system. If DSCK is asserted throughout SRESET assertion
and then past SRESET negation, the processor takes a breakpoint
exception and goes directly to debug mode instead of fetching the reset
vector. To avoid entering debug mode after reset, DSCK must be negated
no later than seven clock cycles after SRESET negates, allowing the
processor to jump to the reset vector and begin normal execution. If
debug mode is entered immediately after reset, as shown in Figure 44-7,
ICR[DPI] is set. The user can enable events that can initiate debug mode
and determine which events require regular interrupt handling.

Re: Enabling 8xx debug mode

[Dan Malek]

On Aug 22, 2005, at 10:20 PM, Marcelo Tosatti wrote:

> I know now that the BDI automatically enables debug mode by asserting
> the DSCK signal (available through the JTAG port). Is there any way
> to enable debugging mode purely via software?

I'm not sure I really understand the question, but I'll give some
answers anyway :-)  The 8xx has the development/debug support,
which is a bunch of registers that allow setting instruction/data
breakpoints and so on.  These are accessible from software, along
with other standard PowerPC debug (like single step).

The DSCK is a BDM/JTAG clock signal, and along with the other
signals allow the clocking of instructions and data through the BDM
pins.  One of the things you can do is strobe in instructions that will
set these same breakpoint or other debug registers as are accessible
from software running on the part.

So, if you have software running on the processor, you can do the
same things.  Obviously, if you are stuck someplace you need to
get the attention of the processor.  You can do this with some interrupt
like kgdb does, then use the debug interface to help.

Does this make sense?

Thanks.

	-- Dan

Re: Enabling 8xx debug mode

[Marcelo Tosatti]

On Tue, Aug 23, 2005 at 12:58:21AM -0400, Dan Malek wrote:
> 
> On Aug 22, 2005, at 10:20 PM, Marcelo Tosatti wrote:
> 
> >I know now that the BDI automatically enables debug mode by asserting
> >the DSCK signal (available through the JTAG port). Is there any way
> >to enable debugging mode purely via software?
> 
> I'm not sure I really understand the question, but I'll give some
> answers anyway :-)  The 8xx has the development/debug support,
> which is a bunch of registers that allow setting instruction/data
> breakpoints and so on.  These are accessible from software, along
> with other standard PowerPC debug (like single step).
> 
> The DSCK is a BDM/JTAG clock signal, and along with the other
> signals allow the clocking of instructions and data through the BDM
> pins.  One of the things you can do is strobe in instructions that will
> set these same breakpoint or other debug registers as are accessible
> from software running on the part.
> 
> So, if you have software running on the processor, you can do the
> same things.  Obviously, if you are stuck someplace you need to
> get the attention of the processor.  You can do this with some interrupt
> like kgdb does, then use the debug interface to help.
> 
> Does this make sense?

Yep.. my misunderstanding was the debug mode can only be turned ON by
asserting the DSCK signal during SRESET as the manual says.

That's fine.

I'm trying to use the debugging registers - seem to work (the example
is a data breakpoint). Just need a real interrupt handler, the current
one breaks  at trap but since the console is not yet initialized I 
et no output (that sucks).

It panic()'s, as expected.


Index: arch/ppc/boot/simple/head.S
===================================================================
RCS file: /mnt/test1/tslinux_mv21/linux-2.6/arch/ppc/boot/simple/head.S,v
retrieving revision 1.3
diff -u -r1.3 head.S
--- arch/ppc/boot/simple/head.S	16 Mar 2005 22:04:09 -0000	1.3
+++ arch/ppc/boot/simple/head.S	23 Aug 2005 01:41:07 -0000
@@ -130,7 +130,18 @@
 	 * processor correctly. Don't do this if you want to debug
 	 * using a BDM device.
 	 */
+#define CONFIG_8xx_DEBUG
+#ifdef CONFIG_8xx_DEBUG
+	/* bit 2: Checkstop enable
+	 * bit 3: Machine check interrupt enable
+	 * bits [28,30]: load/store, instruction and external breakpoint resp.
+	 * bit 31: Development port nonmaskable request enable
+	 */
+	li	r4,0x000F
+	lis	r4,0x3000
+#else
 	li	r4,0		/* Zero DER to prevent FRZ */
+#endif
 	mtspr	SPRN_DER,r4
 #endif
 
Index: arch/ppc/kernel/head_8xx.S
===================================================================
RCS file: /mnt/test1/tslinux_mv21/linux-2.6/arch/ppc/kernel/head_8xx.S,v
retrieving revision 1.4
diff -u -r1.4 head_8xx.S
--- arch/ppc/kernel/head_8xx.S	16 Mar 2005 22:04:09 -0000	1.4
+++ arch/ppc/kernel/head_8xx.S	23 Aug 2005 03:05:35 -0000
@@ -554,7 +554,17 @@
  * support of breakpoints and such.  Someday I will get around to
  * using them.
  */
-	EXCEPTION(0x1c00, Trap_1c, UnknownException, EXC_XFER_EE)
+. = 0x1c00
+DataBreakpoint:
+
+	EXCEPTION_PROLOG
+	mfspr r4,DAR
+	stw r4,_DAR(r11)
+	mfspr r5,DSISR
+	stw r5,_DSISR(r11)
+	trap
+
+/*	EXCEPTION(0x1c00, Trap_1c, UnknownException, EXC_XFER_EE) */
 	EXCEPTION(0x1d00, Trap_1d, UnknownException, EXC_XFER_EE)
 	EXCEPTION(0x1e00, Trap_1e, UnknownException, EXC_XFER_EE)
 	EXCEPTION(0x1f00, Trap_1f, UnknownException, EXC_XFER_EE)
Index: arch/ppc/kernel/misc.S
===================================================================
RCS file: /mnt/test1/tslinux_mv21/linux-2.6/arch/ppc/kernel/misc.S,v
retrieving revision 1.4
diff -u -r1.4 misc.S
--- arch/ppc/kernel/misc.S	21 Jun 2005 16:43:24 -0000	1.4
+++ arch/ppc/kernel/misc.S	22 Aug 2005 23:23:06 -0000
@@ -1276,6 +1276,31 @@
 	addi	r1,r1,16
 	blr
 
+#define LCTRL1	156
+#define LCTRL2	157
+#define CMPE	152
+#define CMPF	153
+
+/* initrd_watchpoint(unsigned long start, unsigned long end) */
+_GLOBAL(initrd_watchpoint)
+	stw	r5, 4(r0)
+
+	mtspr	CMPE, r3
+	mtspr	CMPF, r4
+
+	li 	r5, 0x0000
+	lis	r5, 0xD4F0
+
+	mtspr	LCTRL1,	r5
+
+	li 	r5, 0x0002
+	lis	r5, 0x8A00
+
+	mtspr	LCTRL2, r5
+
+	lwz	r5, 4(r0)
+	blr
+
 /*
  * This routine is just here to keep GCC happy - sigh...
  */
Index: arch/ppc/syslib/m8xx_setup.c
===================================================================
RCS file: /mnt/test1/tslinux_mv21/linux-2.6/arch/ppc/syslib/m8xx_setup.c,v
retrieving revision 1.12
diff -u -r1.12 m8xx_setup.c
--- arch/ppc/syslib/m8xx_setup.c	30 Jun 2005 23:02:49 -0000	1.12
+++ arch/ppc/syslib/m8xx_setup.c	23 Aug 2005 03:08:27 -0000
@@ -70,6 +70,8 @@
 
 unsigned char __res[sizeof(bd_t)];
 
+extern void initrd_watchpoint(unsigned long start, unsigned long end);
+
 extern void m8xx_ide_init(void);
 
 extern unsigned long find_available_memory(void);
@@ -618,6 +620,9 @@
 	}
 #endif /* CONFIG_BLK_DEV_INITRD */
 	/* take care of cmd line */
+	
+	//initrd_watchpoint(initrd_start, initrd_end);
+	
 	if ( r6 )
 	{
 		*(char *)(r7+KERNELBASE) = 0;
diff -u -r1.6 main.c
--- init/main.c	14 Jun 2005 18:17:07 -0000	1.6
+++ init/main.c	23 Aug 2005 03:08:10 -0000
@@ -453,6 +453,8 @@
  *	Activate the first processor.
  */
 
+extern void initrd_watchpoint(unsigned long start, unsigned long end);
+
 asmlinkage void __init start_kernel(void)
 {
 	char * command_line;
@@ -495,6 +497,7 @@
 		   __stop___param - __start___param,
 		   &unknown_bootoption);
 	sort_main_extable();
+	initrd_watchpoint(initrd_start, initrd_end);	
 	trap_init();
 	rcu_init();
 	init_IRQ();

Re: Enabling 8xx debug mode

[Dan Malek]

On Aug 23, 2005, at 1:31 AM, Marcelo Tosatti wrote:

> I'm trying to use the debugging registers - seem to work (the example
> is a data breakpoint). Just need a real interrupt handler,...

yes, that's the right idea.  It's easier with a BDI2000, though :-)

Have fun!

	-- Dan

client and server implementation

[Saini Narendra]

For one perticular implementation, I need to work on a client
and server program on 8xx family of ppc. One of the main goal is
to keep the code size minimum. Has anyone already implemented
similar things on ppc. Can anyone give me pointers for the same.

Also, is there any trimmed version of pcap and libnet available
for 8xx ppc?

-sainink


		
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