Re: Chenging 2 bits in MSR in ppc6xx_idle() with 1 command?

[Segher Boessenkool <segher@kernel.crashing.org>]

>>> Whereas MPC8245's user manual says, that when setting the MSR_POW 
>>> bit in
>>> the MSR one may not set any other bit in it with the same 
>>> instruction.
>>> Does this mean that the above does not actually work on those (and
>>> similar) CPUs or does it work because of the loop?
>>
>> That doc bit looks a bit strange. The kernel pretty much relies on
>> setting MSR:EE and MSR:POW atomicaly.
>
> Hm, wouldn't it just work? In ppc6xx_idle() the _TLF_NAPPING bit is 
> set.
> If as a result of mtmsr only the EE bit is set and we get an interrupt,

But what if only the POW flag gets set, and EE doesn't?
That's one CPU that won't wake up anymore :-/

It sounds like changing the sequence to first set EE, sync,
isync, and only then set POW as well will work safely on all
hardware?


Segher