From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from wa-out-1112.google.com (wa-out-1112.google.com [209.85.146.177]) by ozlabs.org (Postfix) with ESMTP id 3B425DDE1F for ; Thu, 28 Aug 2008 10:21:30 +1000 (EST) Received: by wa-out-1112.google.com with SMTP id n7so55386wag.13 for ; Wed, 27 Aug 2008 17:21:28 -0700 (PDT) Message-ID: Date: Wed, 27 Aug 2008 17:21:28 -0700 From: vb Sender: vbendeb@gmail.com To: "Roland Dreier" Subject: Re: mmap and ppc460gt In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 References: <200808271013.18659.arnd@arndb.de> Cc: Arnd Bergmann , linuxppc-embedded@ozlabs.org List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Wed, Aug 27, 2008 at 5:11 PM, Roland Dreier wrote: > > The problem now is that that PCI register space gets mapped with > > caching enabled (by looking at the TLB contents), so I still can't > > control the device. I did some search and indeed UIO device driver > > came up, I'll read the article. I was wondering though if there is a > > simpler way to modify cache attributes of a region. mmap() doesn't > > seem to provide an interface for that, is there some other function to > > call to configure 'cache inhibit' attribute for a region? > > The issue would be related to phys_mem_access_prot() not doing the right > thing in this case. In fact it looks like the arch/powerpc > page_is_ram() implementation has the same bug that I fixed a long time > ago for arch/ppc in 8b150478 ("[PATCH] ppc: make phys_mem_access_prot() > work with pfns instead of addresses"). I'll send a patch a little later > that you can try out. > Ronald, I will appreciate the patch that very much! TIA, /vb > - R. >