From: Balbir Singh <bsingharora@gmail.com>
To: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>,
benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH v5 1/7] powerpc/mm: update ptep_set_access_flag to not do full mm tlb flush
Date: Thu, 24 Nov 2016 02:21:56 +1100 [thread overview]
Message-ID: <f6825375-404f-7030-3b59-f75c7c50b98b@gmail.com> (raw)
In-Reply-To: <87shqigt67.fsf@linux.vnet.ibm.com>
On 24/11/16 01:36, Aneesh Kumar K.V wrote:
> Balbir Singh <bsingharora@gmail.com> writes:
>
>> On 23/11/16 22:53, Aneesh Kumar K.V wrote:
>>> Balbir Singh <bsingharora@gmail.com> writes:
>>>
>>>> On 23/11/16 22:09, Aneesh Kumar K.V wrote:
>>>>> When we are updating pte, we just need to flush the tlb mapping for
>>>>> that pte. Right now we do a full mm flush because we don't track page
>>>>> size. Update the interface to track the page size and use that to
>>>>> do the right tlb flush.
>>>>>
>>>>
>>>> Could you also clarify the scope -- this seems to be _radix_ only.
>>>> The problem statement is not very clear and why doesn't the flush_tlb_page()
>>>> following ptep_set_access_flags() work? What else do we need to do?
>>>
>>> Yes it modifies only radix part. Don't understand the flush_tlb_page()
>>> part of the comment above. We are modifying the tlbflush that we need to do in the pte update
>>> sequence for DD1. ie, we need to do the flush before we can set the pte
>>> with new value.
>>>
>>> Also in this specific case, we can idealy drop that flush_tlb_page,
>>> because relaxing an access really don't need a tlb flush from generic
>>> architecture point of view. I left it there to make sure, we measure and
>>> get the invalidate path correct before going ahead with that
>>> optimization.
>>>
>>
>> OK.. here is my untested solution. I've only compiled it.
>> It breaks the 64/hash/radix abstractions, but it makes the
>> changes much simpler
>>
>> Signed-off-by: Balbir Singh <bsingharora@gmail.com>
>
> I find the below one more confusing and complicated, spreading the
> details of DD1 around the code. I am not sure what extra i could have
> done to simplify the code. We have done the arch pte updates such that
> most of the update use the pte_update() interface and the one which relax
> the access bits get to ptep_set_access_flag. All pte updated rules are
> contained there. What you did below is that you moved the dd1 sequence
> out to a place where page size is available. What I did in my patch is to
> pass page size around. IMHO it is a matter of style. I also want to pass
> page size around so that we keep huge_pte_update, pte_update,
> ptep_set_access_flags all similar.
>
Agreed and the reason I did it that way is that after a while we know
the _dd1_ variants need not be supported/maintained at all. It is a
matter of style and I was wondering if we need to change the API
to pass address and page_size as a permanent solution.
Balbir Singh.
next prev parent reply other threads:[~2016-11-23 15:21 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-23 11:09 [PATCH v5 1/7] powerpc/mm: update ptep_set_access_flag to not do full mm tlb flush Aneesh Kumar K.V
2016-11-23 11:09 ` [PATCH v5 2/7] powerpc/mm: Rename hugetlb-radix.h to hugetlb.h Aneesh Kumar K.V
2016-11-23 11:09 ` [PATCH v5 3/7] powerpc/mm/hugetlb: Handle hugepage size supported by hash config Aneesh Kumar K.V
2016-11-23 14:08 ` Balbir Singh
2016-11-23 14:30 ` Aneesh Kumar K.V
2016-11-23 11:10 ` [PATCH v5 4/7] powerpc/mm/hugetlb: Make copy of huge_ptep_get_and_clear to different platform headers Aneesh Kumar K.V
2016-11-23 11:10 ` [PATCH v5 5/7] powerpc/mm/hugetlb: Switch hugetlb update to use huge_pte_update Aneesh Kumar K.V
2016-11-23 11:10 ` [PATCH v5 6/7] powerpc/mm: update pte_update to not do full mm tlb flush Aneesh Kumar K.V
2016-11-23 11:10 ` [PATCH v5 7/7] powerpc/mm: Batch tlb flush when invalidating pte entries Aneesh Kumar K.V
2016-11-23 11:23 ` [PATCH v5 1/7] powerpc/mm: update ptep_set_access_flag to not do full mm tlb flush Balbir Singh
2016-11-23 11:53 ` Aneesh Kumar K.V
2016-11-23 14:05 ` Balbir Singh
2016-11-23 14:36 ` Aneesh Kumar K.V
2016-11-23 15:21 ` Balbir Singh [this message]
2016-11-25 2:48 ` Paul Mackerras
2016-11-25 4:19 ` Aneesh Kumar K.V
2016-11-25 7:05 ` Aneesh Kumar K.V
2016-11-25 8:22 ` Benjamin Herrenschmidt
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