From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from yx-out-2324.google.com (yx-out-2324.google.com [74.125.44.29]) by ozlabs.org (Postfix) with ESMTP id CB55EDDDF0 for ; Sun, 3 May 2009 14:26:08 +1000 (EST) Received: by yx-out-2324.google.com with SMTP id 8so1775306yxb.39 for ; Sat, 02 May 2009 21:26:06 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <625fc13d0904200529l152b8d75g33c3f940de1b2920@mail.gmail.com> <1240388476.17445.10.camel@pasglop> <1241126291.29501.41.camel@pasglop> Date: Sun, 3 May 2009 00:26:05 -0400 Message-ID: Subject: Re: Porting the ibm_newemac driver to use phylib (and other PHY/MAC questions) From: Kyle Moffett To: Benjamin Herrenschmidt Content-Type: text/plain; charset=UTF-8 Cc: netdev , "Linux-Kernel@Vger. Kernel. Org" , linuxppc-dev@ozlabs.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Thu, Apr 30, 2009 at 6:21 PM, Kyle Moffett wrote: >>> I'm also curious about the intent of the "mdio_instance" pointer (IE: >>> the "mdio-device" property). =C2=A0Is that used when all the PHY device= s >>> are attached to the MDIO bus of only one of the (multiple) emac >>> devices? >> >> It's common especially on older SoCs using EMAC to have only one of >> the EMAC instance with an MDIO bus for configuring the PHYs. This is one >> of the reasons why I have the mutex in the low level MDIO access >> routines since 2 EMACs can try to talk to the same MDIO, and this is the >> problem I had with phylib back then which was doing everything in atomic >> contexts. > > Ok, good, the current mdiobus code seems to make handling this a good > deal easier. Ok, I've dug through the docs on the 460EPx (the CPU I'm using), and I'd like some confirmation of the following: * The EMAC hardware itself internally has its own dedicated MDIO/MDClk lines, driven by the STACR register. * On many/most cpus, there is only a single set of external MDIO/MDClk pins, driven either off the ZMII bridge or the RGMII bridge. * Both bridge-types have their own internal register for switching the external MDIO/MDClk pins between the two sets of internal EMAC<=3D>bridge links. * Some SoCs have both an ZMII and an RGMII bridge, and the external MDIO/MDClk pins are only connected to one of the two bridges (How do I know which one? Alternatively, do I just program both and hope for the best?). * Some older SoCs simply export the MDIO/MDClk pins from one of their internal EMAC chips and don't bother with running it through the multiplexing bridge. Are there any SoCs which actually export the MDIO/MDClk pins from both/all of their EMACs? Cheers, Kyle Moffett