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From: Dan Malek <dan@embeddededge.com>
To: Eugene Surovegin <ebs@ebshome.net>
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: [PATCH 1/3] SPI bus core infrastructure
Date: Sat, 23 Jul 2005 11:11:57 -0400	[thread overview]
Message-ID: <f9aee3d7921497b1309fb9c67caa914c@embeddededge.com> (raw)
In-Reply-To: <20050723142210.GA24313@gate.ebshome.net>


On Jul 23, 2005, at 10:22 AM, Eugene Surovegin wrote:

> This isn't enough.
>
> You must have a way to specify clock frequency, data order (which bit
> goes first, char length.

...  and there is more.  Some devices, even when not selected, still
use the SPI clock for clocking internal logic.  You have to ensure with
such devices you don't ever run the SPI faster than their spec.  This
is application specific, but something that has to be considered when
there are multiple devices on the SPI bus.

Also, many boards use external logic for the assertion of the
device select, which is necessary if there is more than one device
on the bus.  Sometimes it's a multiplexer that routes the controller
SPI select, other times the multiplexer drives the selects directly.
In my review of the patch, I didn't see anything that would provide
for this.

I think the SPI driver is a great idea, I hope we can find a way
to make it work at least as well as the I2C.

Thanks!


	-- Dan

  reply	other threads:[~2005-07-23 15:11 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2005-07-23 14:07 [PATCH 1/3] SPI bus core infrastructure Grant Likely
2005-07-23 14:22 ` Eugene Surovegin
2005-07-23 15:11   ` Dan Malek [this message]
2005-07-25  8:38     ` Kate Alhola

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