[PATCH v2][POWERPC] document ipic level/sense info

[PATCH v2][POWERPC] document ipic level/sense info

[Stuart Yoder]

document level and sense information for the Freescale
IPIC interrupt controller

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
---
 Documentation/powerpc/booting-without-of.txt |   18 +++++++++++++++++-
 1 files changed, 17 insertions(+), 1 deletions(-)

diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index c169299..7ad9e42 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -50,13 +50,14 @@ Table of Contents
       g) Freescale SOC SEC Security Engines
       h) Board Control and Status (BCSR)
       i) Freescale QUICC Engine module (QE)
-      g) Flash chip nodes
+      j) Flash chip nodes
 
   VII - Specifying interrupt information for devices
     1) interrupts property
     2) interrupt-parent property
     3) OpenPIC Interrupt Controllers
     4) ISA Interrupt Controllers
+    5) IPIC Interrupt Controllers
 
   Appendix A - Sample SOC node for MPC8540
 
@@ -1878,6 +1879,21 @@ encodings listed below:
 	2 =  high to low edge sensitive type enabled
 	3 =  low to high edge sensitive type enabled
 
+5) Freescale IPIC Interrupt Controllers
+---------------------------------------
+
+IPIC interrupt controllers are specific to Freescale 83xx
+SOCs.  Two cells are required to encode interrupt information.
+The first cell defines the interrupt number.  The second cell
+defines the sense and level information.
+
+Sense and level information follows the Linux convention
+(specified in include/linux/interrupt.h) and should be encoded
+as follows:
+
+	2 =  high to low edge sensitive type enabled
+	8 =  active low level sensitive type enabled
+
 
 Appendix A - Sample SOC node for MPC8540
 ========================================
-- 
1.5.0.3

Re: [PATCH v2][POWERPC] document ipic level/sense info

[Grant Likely]

On 7/9/07, Stuart Yoder <b08248@freescale.com> wrote:
>
> document level and sense information for the Freescale
> IPIC interrupt controller
>
> +Sense and level information follows the Linux convention
> +(specified in include/linux/interrupt.h) and should be encoded
> +as follows:
> +
> +       2 =  high to low edge sensitive type enabled
> +       8 =  active low level sensitive type enabled
> +

... but it is probably worthwhile commentting that sense types 1 & 4
are not supported; just to fill in the obvious gaps.  :-)

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195

Re: [PATCH v2][POWERPC] document ipic level/sense info

[Segher Boessenkool]

>> +Sense and level information follows the Linux convention
>> +(specified in include/linux/interrupt.h) and should be encoded
>> +as follows:
>> +
>> +       2 =  high to low edge sensitive type enabled
>> +       8 =  active low level sensitive type enabled

> ... but it is probably worthwhile commentting that sense types 1 & 4
> are not supported; just to fill in the obvious gaps.  :-)

Same for sense types 0, 3, 5, 6, ...

Just name the sense types 0 and 1, similar to what all other
OF interrupt controller bindings do.


Segher

RE: [PATCH v2][POWERPC] document ipic level/sense info

[Yoder Stuart-B08248]

=20

> -----Original Message-----
> From: Segher Boessenkool [mailto:segher@kernel.crashing.org]=20
> Sent: Tuesday, July 10, 2007 8:21 AM
> To: Grant Likely
> Cc: Yoder Stuart-B08248; linuxppc-dev@ozlabs.org; paulus@samba.org
> Subject: Re: [PATCH v2][POWERPC] document ipic level/sense info
>=20
> >> +Sense and level information follows the Linux convention
> >> +(specified in include/linux/interrupt.h) and should be encoded
> >> +as follows:
> >> +
> >> +       2 =3D  high to low edge sensitive type enabled
> >> +       8 =3D  active low level sensitive type enabled
>=20
> > ... but it is probably worthwhile commentting that sense types 1 & 4
> > are not supported; just to fill in the obvious gaps.  :-)
>=20
> Same for sense types 0, 3, 5, 6, ...
>=20
> Just name the sense types 0 and 1, similar to what all other
> OF interrupt controller bindings do.

Actually, all I am trying to do with this patch is document the
current state of things.  The 2/8 sense type usage has been that
way for a long time, and I'll defer to the 83xx maintainers
if they see any value in changing it.

Right now there are many DTS files with level/sense set to values
like 8 and no indication anywhere where those values came from.

Stuart

Re: [PATCH v2][POWERPC] document ipic level/sense info

[Kumar Gala]

On Jul 10, 2007, at 8:21 AM, Segher Boessenkool wrote:

>>> +Sense and level information follows the Linux convention
>>> +(specified in include/linux/interrupt.h) and should be encoded
>>> +as follows:
>>> +
>>> +       2 =  high to low edge sensitive type enabled
>>> +       8 =  active low level sensitive type enabled
>
>> ... but it is probably worthwhile commentting that sense types 1 & 4
>> are not supported; just to fill in the obvious gaps.  :-)
>
> Same for sense types 0, 3, 5, 6, ...
>
> Just name the sense types 0 and 1, similar to what all other
> OF interrupt controller bindings do.

I'm not really keen on changing the values at this point.  I think we  
are stuck with them.

- k

Re: [PATCH v2][POWERPC] document ipic level/sense info

[Segher Boessenkool]

>>>> +Sense and level information follows the Linux convention
>>>> +(specified in include/linux/interrupt.h) and should be encoded
>>>> +as follows:
>>>> +
>>>> +       2 =  high to low edge sensitive type enabled
>>>> +       8 =  active low level sensitive type enabled
>>
>>> ... but it is probably worthwhile commentting that sense types 1 & 4
>>> are not supported; just to fill in the obvious gaps.  :-)
>>
>> Same for sense types 0, 3, 5, 6, ...
>>
>> Just name the sense types 0 and 1, similar to what all other
>> OF interrupt controller bindings do.
>
> Actually, all I am trying to do with this patch is document the
> current state of things.  The 2/8 sense type usage has been that
> way for a long time, and I'll defer to the 83xx maintainers
> if they see any value in changing it.
>
> Right now there are many DTS files with level/sense set to values
> like 8 and no indication anywhere where those values came from.

Ah right, too bad then.  Just document that only 2 and 8 make
sense on current hardware, in that case.


Segher

Re: [PATCH v2][POWERPC] document ipic level/sense info

[Segher Boessenkool]

>>> ... but it is probably worthwhile commentting that sense types 1 & 4
>>> are not supported; just to fill in the obvious gaps.  :-)
>>
>> Same for sense types 0, 3, 5, 6, ...
>>
>> Just name the sense types 0 and 1, similar to what all other
>> OF interrupt controller bindings do.
>
> I'm not really keen on changing the values at this point.  I think  
> we are stuck with them.

Yeah, unless you create a new binding for the same hardware.
Not that I recommend that of course.  I suppose the lesson
is to document a device binding as soon as possible, not
months after the corresponding code and trees are out (or to
mark all such code/trees clearly as "preliminary").


Segher